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1.  Origin of Anomalous Piezoresistive Effects in VLS Grown Si Nanowires 
Nano Letters  2015;15(3):1780-1785.
Although the various effects of strain on silicon are subject of intensive research since the 1950s the physical background of anomalous piezoresistive effects in Si nanowires (NWs) is still under debate. Recent investigations concur in that due to the high surface-to-volume ratio extrinsic surface related effects superimpose the intrinsic piezoresistive properties of nanostructures. To clarify this interplay of piezoresistive effects and stress related surface potential modifications, we explored a particular tensile straining device (TSD) with a monolithic embedded vapor–liquid–solid (VLS) grown Si NW. Integrating the suspended NW in a gate all around (GAA) field effect transistor (FET) configuration with a transparent gate stack enables optical and field modulated electrical characterization under high uniaxial tensile strain applied along the ⟨111⟩ Si NW growth direction. A model based on stress-induced carrier mobility change and surface charge modulation is proposed to interpret the actual piezoresistive behavior of Si NWs. By controlling the nature and density of surface states via passivation the “true” piezoresistance of the NWs is found to be comparable with that of bulk Si. This demonstrates the indispensability of application-specific NW surface conditioning and the modulation capability of Si NWs properties for sensor applications.
PMCID: PMC4358075  PMID: 25651106
Silicon; nanowire; VLS growth; piezoresistance; surface doping
2.  Impact of oxidation and reduction annealing on the electrical properties of Ge/La2O3/ZrO2 gate stacks 
Solid-State Electronics  2012;74(5):7-12.
► Ge surface passivation by scalable multilayer of La2O3/ZrO2. ► LaxGeyOz interfacial layers thickness controllable by oxidation time. ► Forming gas annealing improves Dit down to 3 × 1011 eV−1 cm−2 in presence of LaxGeyOz interlayer. ► Trade-off between interface trap density and equivalent oxide thickness.
The paper addresses the passivation of Germanium surfaces by using layered La2O3/ZrO2 high-k dielectrics deposited by Atomic Layer Deposition to be applied in Ge-based MOSFET devices. Improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing ambient during thermal post treatment in presence of thin Pt cap layers are demonstrated. The results suggest the formation of thin intermixed LaxGeyOz interfacial layers with thicknesses controllable by oxidation time. This formation is further investigated by XPS, EDX/EELS and TEM analysis. An additional reduction annealing treatment further improves the electrical properties of the gate dielectrics in contact with the Ge substrate. As a result low interface trap densities on (1 0 0) Ge down to 3 × 1011 eV−1 cm−2 are demonstrated. The formation of the high-k LaxGeyOz layer is in agreement with the oxide densification theory and may explain the improved interface trap densities. The scaling potential of the respective layered gate dielectrics used in Ge-based MOS-based device structures to EOT of 1.2 nm or below is discussed. A trade-off between improved interface trap density and a lowered equivalent oxide thickness is found.
PMCID: PMC3587347  PMID: 23483756
High-k; La2O3; ZrO2; Annealing; Oxidation; Germanate; Germanium
3.  Synthesis and electrical characterization of intrinsic and in situ doped Si nanowires using a novel precursor 
Perchlorinated polysilanes were synthesized by polymerization of tetrachlorosilane under cold plasma conditions with hydrogen as a reducing agent. Subsequent selective cleavage of the resulting polymer yielded oligochlorosilanes SinCl2 n +2 (n = 2, 3) from which the octachlorotrisilane (n = 3, Cl8Si3, OCTS) was used as a novel precursor for the synthesis of single-crystalline Si nanowires (NW) by the well-established vapor–liquid–solid (VLS) mechanism. By adding doping agents, specifically BBr3 and PCl3, we achieved highly p- and n-type doped Si-NWs by means of atmospheric-pressure chemical vapor deposition (APCVD). These as grown NWs were investigated by means of scanning electron microscopy (SEM) and transmission electron microscopy (TEM), as well as electrical measurements of the NWs integrated in four-terminal and back-gated MOSFET modules. The intrinsic NWs appeared to be highly crystalline, with a preferred growth direction of [111] and a specific resistivity of ρ = 6 kΩ·cm. The doped NWs appeared to be [112] oriented with a specific resistivity of ρ = 198 mΩ·cm for p-type Si-NWs and ρ = 2.7 mΩ·cm for n-doped Si-NWs, revealing excellent dopant activation.
PMCID: PMC3458602  PMID: 23019552
chemical vapour deposition; field-effect transistor; oligosilanes; radiation-induced nanostructures; silicon nanowires; vapor–liquid–solid mechanism
4.  Multimode Silicon Nanowire Transistors 
Nano Letters  2014;14(11):6699-6703.
The combined capabilities of both a nonplanar design and nonconventional carrier injection mechanisms are subject to recent scientific investigations to overcome the limitations of silicon metal oxide semiconductor field effect transistors. In this Letter, we present a multimode field effect transistors device using silicon nanowires that feature an axial n-type/intrinsic doping junction. A heterostructural device design is achieved by employing a self-aligned nickel-silicide source contact. The polymorph operation of the dual-gate device enabling the configuration of one p- and two n-type transistor modes is demonstrated. Not only the type but also the carrier injection mode can be altered by appropriate biasing of the two gate terminals or by inverting the drain bias. With a combined band-to-band and Schottky tunneling mechanism, in p-type mode a subthreshold swing as low as 143 mV/dec and an ON/OFF ratio of up to 104 is found. As the device operates in forward bias, a nonconventional tunneling transistor is realized, enabling an effective suppression of ambipolarity. Depending on the drain bias, two different n-type modes are distinguishable. The carrier injection is dominated by thermionic emission in forward bias with a maximum ON/OFF ratio of up to 107 whereas in reverse bias a Schottky tunneling mechanism dominates the carrier transport.
PMCID: PMC4245716  PMID: 25303290
Silicon nanowire; reconfigurable transistor; dual-gate; Schottky barrier tunneling; band-to-band tunneling; nickel silicide
5.  Free-Standing Magnetic Nanopillars for 3D Nanomagnet Logic 
ACS Applied Materials & Interfaces  2014;6(22):20254-20260.
Nanomagnet logic (NML) is a relatively new computation technology that uses arrays of shape-controlled nanomagnets to enable digital processing. Currently, conventional resist-based lithographic processes limit the design of NML circuitry to planar nanostructures with homogeneous thicknesses. Here, we demonstrate the focused electron beam induced deposition of Fe-based nanomaterial for magnetic in-plane nanowires and out-of-plane nanopillars. Three-dimensional (3D) NML was achieved based on the magnetic coupling between nanowires and nanopillars in a 3D array. Additionally, the same Fe-based nanomaterial was used to produce tilt-corrected high-aspect-ratio probes for the accurate magnetic force microscopy (MFM) analysis of the fabricated 3D NML gate arrays. The interpretation of the MFM measurements was supported by magnetic simulations using the Object Oriented MicroMagnetic Framework. Introducing vertical out-of-plane nanopillars not only increases the packing density of 3D NML but also introduces an extra magnetic degree of freedom, offering a new approach to input/output and processing functionalities in nanomagnetic computing.
PMCID: PMC4251043  PMID: 25296008
nanomagnet logic; electron beam induced deposition; iron; magnetic nanowires; nanomagnetism; MFM; computational nanotechnology

Results 1-5 (5)