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Nanoscale Res Lett. 2017; 12: 198.
Published online 2017 March 16. doi:  10.1186/s11671-017-1958-3
PMCID: PMC5355408

Design of High Performance Si/SiGe Heterojunction Tunneling FETs with a T-Shaped Gate


In this paper, a new Si/SiGe heterojunction tunneling field-effect transistor with a T-shaped gate (HTG-TFET) is proposed and investigated by Silvaco-Atlas simulation. The two source regions of the HTG-TFET are placed on both sides of the gate to increase the tunneling area. The T-shaped gate is designed to overlap with N+ pockets in both the lateral and vertical directions, which increases the electric field and tunneling rate at the top of tunneling junctions. Moreover, using SiGe in the pocket regions leads to the smaller tunneling distance. Therefore, the proposed HTG-TFET can obtain the higher on-state current. The simulation results show that on-state current of HTG-TFET is increased by one order of magnitude compared with that of the silicon-based counterparts. The average subthreshold swing (SS) of HTG-TFET is 44.64 mV/dec when V g is varied from 0.1 to 0.4 V, and the point SS is 36.59 mV/dec at V g = 0.2 V. Besides, this design cannot bring the sever Miller capacitance for the TFET circuit design. By using the T-shaped gate and SiGe pocket regions, the overall performance of the TFET is optimized.

Keywords: Band-to-band tunneling (BTBT), T-shaped gate, Tunneling field-effect transistor (TFET), Heterojunction


Tunneling field-effect transistor (TFET) has become a kind of potential electric device for the ultralow power consumption applications [13]. Because band-to-band tunneling (BTBT) is the main operation mechanism in TFETs, TFETs can break the limitation of 60 mV/dec subthreshold swing (SS) in the conventional CMOS field-effect transistor that relies on the hot electron emission [46]. In addition, TFETs are less influenced by short channel effects than MOSFETs. However, the low on-state current is an inherent disadvantage in the traditional TFETs. In order to improve the on-state current of TFETs, various novel device structures have been proposed such as L-shaped channel TFET (LTFET) [7, 8], U-shaped channel TFET (UTFET) [9], L-shaped gate TFET (LG-TFET) [10], heterojunction TFET (HTFET) [11, 12]. Among these structures, the LG-TFET is proved to be essential for the enhancement of on-state current, because its tunneling current mainly depends on the electron BTBT perpendicular to the channel instead of parallel to the channel, and gate-pocket overlap regions in the lateral direction increase the electric field at the top of tunneling junction, which is helpful for the improvement of on-state current [10, 13, 14]. But electron BTBT in LG-TFET occurs only on one side of the gate, which will limit further improvement of on-state current.

In order to solve the above problem, a new heterojunction TFET with a T-shaped gate (HTG-TFET) is proposed. The proposed device structure remains vertical tunneling and places two source regions on both sides of the gate to further increase tunneling area. The T-shaped gate overlaps with the pocket regions in the lateral direction to increase the electric field at the top of tunneling junction. In addition, the heterojunctions between SiGe pocket regions and silicon source regions promote energy band to bend sharply [15]. TCAD simulation results show that proposed HTG-TFET gains higher on-state current and lower SS than both LG-TFET and UTFET.


The HTG-TFET discussed in this paper is illustrated in Fig. 1a. Compared with the conventional planar TFET, the HTG-TFET uses the recessed channel on the substrate to transform point tunneling parallel to channel into line tunneling perpendicular to channel, which increases the tunneling area and on-state current. Unlike the LG-TFET and UTFET shown in Fig. 1b, c, the HTG-TFET applies the dual sources to increase the tunneling area and its drain is placed at the bottom of the devices to decrease the gate-drain capacitance (C gd). Its gate overlaps with N+ pockets in both the vertical and the lateral directions. Therefore, the gate of HTG-TFET resembles the alphabet “T.” As shown in Fig. 2, using this structure, both the line tunneling and the point tunneling simultaneously take place on both sides of gate, which can enhance on-state current. In addition, the gate-pocket overlap in the lateral direction increases the electric field and tunneling area at the top of tunneling junction when the device is turned on. Since high electric field can induce higher BTBT generation rate, the overlap is helpful for the enhancement of the on-state current [9]. There is a lot of work which has demonstrated that heterojunction TFETs consisted of Si, Ge, and SiGe alloys are considered the most promising material system for the TFET due to their natural abundance and well-established fabrication technology; therefore, the pocket regions choose the narrow bandgap SiGe instead of silicon, which decreases tunneling distance to boost on-state current [16].

Fig. 1
Schematic structures of a HTG-TFET, b LG-TFET, and c UTFET
Fig. 2
Schematic of line tunneling and point tunneling in HTG-TFET

The proposed HTG-TFET structure is investigated with Silvaco ATLAS simulation tool using the non-local BTBT model. The non-local BTBT model takes into account the spatial variation of the energy band, and it also considers that the generation/recombination of the opposite carrier type is not spatially coincident. So, the non-local BTBT can model the tunneling process more accurately [17]. A lot of work has demonstrated that TFETs simulated by non-local BTBT are in accord with the experiments [8, 10, 18]. Since the source regions are highly doped, the band gap narrowing model and Fermi-Dirac statistics are included. The Shockley-Read-Hall recombination and Lombardi mobility models are also adopted in the simulations. Moreover, the gate leakage current is ignored.

The simulation parameters of the proposed device are as follows: thickness of the N+ pocket is 5 nm (T p); height of the source regions and drain region is 40 nm (H s) and 20 nm (H d), respectively; length and height of the gate are 10 nm (L g) and 60 nm (H g), respectively; thickness of the gate oxide (HfO2) is 2 nm (T ox); length of gate-pocket overlap is 7 nm (L ov). What is more, gate work function [var phi] is 4.33 eV; doping concentrations of P+ source regions (N s) and N+ drain region (N d) are 1 × 1020/cm3 and 1 × 1018/cm3, respectively; doping concentration of N+ pockets (Np) is 1 × 1019/cm3.

Results and Discussion

Figure 3a shows the transfer characteristics of HTG-TFET, LG-TFET, and UTFET at V d = 0.5 V. It can be seen from Fig. 3a that HTG-TFET has the largest on-state (V d = V g = 0.5 V) drain current and the smallest off-state (V d = 0.5 V, V g = 0 V) drain current due to the improved techniques (dual sources, T-shaped gate, Si/SiGe heterojunction). Compared with the LG-TFET and UTFET, the on-state and off-state drain currents of the HTG-TFET are increased and decreased by about one order of magnitude, respectively. Figure 3a also clearly shows that the average SSs of these three devices are less than 60 mV/dec which is indicated by red dotted line in Fig. 3a. The HTG-TFET obtains the minimum average SS and point SS. The average SSs extracted from 0.1 to 0.4 V are HTG-TFET = 44.64 mV/dec, LG-TFET = 47.21 mV/dec, and UTFET = 46.65 mV/dec; and the point SSs (at Vg = 0.2 V) are HTG-TFET = 36.59 mV/dec, LG-TFET = 46.99 mV/dec, and UTFET = 45.52 mV/dec. The influence of Ge composition in SiGe pocket on the performance of HTG-TFET is shown in Fig. 3b. Obviously, both on-state and off-state currents increase when the Ge composition increases from 0.1 to 0.4. This is due to the fact that band gap of Si1−xGex decreases with increasing Ge composition. Since the highest Ge composition of Si1−xGex is around 40% in industrial production [9], the Ge composition x = 0.3 is regarded as the optimal Ge composition parameter in all the simulations. And Si0.7Ge0.3 pocket can help HTG-TFET to obtain the not only higher on-state current but also lower off-state current.

Fig. 3
a Transfer characteristics of different devices. b Transfer characteristics with different Ge compositions for the HTG-TFET

In order to clearly understand the working mechanism of devices, the energy band diagrams are displayed in Fig. 4 (the inset in the figure shows the location of cutline). From Fig. 4a, b, it can be clearly seen that both point tunneling and line tunneling widths (green dot arrow) are very larger at Vg = 0 V, which makes valance band of source region unable to align with conduction band of pocket so that the off-state current is very low. When the gate voltage rises to 0.3 V and it continues to increase, the tunneling widths obviously decrease due to the sharp bending of energy band. As a result, the drain current increases with the increasing gate voltage. Fortunately, the smaller valence band offset at Si/Si0.7Ge0.3 is found, which does not have a negative effect on device performance. Considering the bandgap narrowing effect caused by heavy doping, the bandgaps of Si and Si0.7Ge0.3 are respectively reduced to 0.96 and 0.82 eV. Besides, the heavily doped Si0.7Ge0.3 pocket makes the energy band of Si0.7Ge0.3 to drop down significantly. Combining the bandgap narrowing effect and heavily doped pocket, such a small valence offset does not create a large barrier to suppress electron to tunnel towards conduction band from valence band. Comparing the energy bands of devices with different pocket materials in Fig. 4c, d, it can be found that tunneling width with Si0.7Ge0.3 pocket is a lot smaller than that that with Si pocket, which is mainly caused by the smaller bandgap of Si0.7Ge0.3. Therefore, the HTG-TFET with Si0.7Ge0.3 pocket can obtain more superior performance than that with silicon pocket.

Fig. 4
The influence of gate voltage on a point tunneling and b line tunneling energy band diagrams; c point tunneling and d line tunneling energy band diagrams of HTG-TFET with different pocket materials

Figure 5 shows the diagrams of electron BTBT rate, total current density, electric field, and potential at V g = 0.5 V and V d = 0.5 V. The electron BTBT rates are shown in Fig. 5a, and the currents flowing from both gate-oxide interfaces to the drain region are shown in Fig. 5b. The gate-pocket overlap regions enhance the gate fringe electric field at the top of tunneling junctions, so the significant bending of potential contour is produced at the top of tunneling junctions, which can be seen in Fig. 5c, d. However, without the lateral gate-pocket overlap regions, the electric field at the top of tunneling junctions does not increase significantly. Therefore, the potential contour does not bend obviously, which is observed from insets in Fig. 5c, d.

Fig. 5
Simulated diagrams of a electron BTBT rate, b total current density, c electric field, and d potential at V g = 0.5 V and V d = 0.5 V

In order to clearly understand that gate-pocket overlap regions can improve the device performance, the electric fields of HTG-TFET with and without overlap in both the lateral and the vertical directions are shown in Fig. 6. Figure 6a reveals that gate-pocket overlap enhances the electric field at the top of tunneling junction. Figure 6b reveals that the HTG-TFET with overlap also gains the greater electric field at pocket-source interface. Considering the strong dependence of energy band on the electric field, the energy band diagrams of HTG-TFET with and without overlap are plotted in Fig. 7a. Due to the enhanced electric field by the overlap, the energy band with overlap bends more sharply than that without overlap. As a result, the overlap causes the larger aligned region of energy bands, which is shown in Fig. 7a. Thus, it is likely that more electrons will tunnel in the device with overlap. This can be demonstrated by the increased tunneling area (at the top of tunneling junction) of the HTG-TFET with overlap in the Fig. 5a. Furthermore, Fig. 7b shows that overlap enhances the electron BTBT rates in the pocket regions. Both the increased tunneling area and tunneling rate are attributed to the increased of the electric field at the top of tunneling junction.

Fig. 6
a Lateral and b vertical electric field of HTG-TFET with and without overlap
Fig. 7
a Energy band diagrams of HTG-TFET with and without overlap. b Electron tunneling rates of HTG-TFET with and without overlap

Figure 8a, b respectively shows the variations of transfer characteristics and on-state drain current with the length of gate-pocket overlap (L ov). The comparison is conducted by keeping the same L g and H g. The drain current increases when the L ov increases from 0 to 7 nm. However, drain current starts to decline when the L ov is larger than 7 nm, which means that drain current reaches the maximum 7.02 μA/μm when the boundaries of the lateral gate align with the source/pocket interfaces. When the L ov is smaller than 7 nm, the reduction of on-state current can easily be explained by the electric field’s lowing near the tunneling junction. However, on-state current also decreases when L ov is greater than 7 nm. This is because the electric field near the tunneling junction does not increase with the further increasing of L ov, whereas, the energy band’s lowing in the source region results in a less steeper bending [10].

Fig. 8
Variations of a transfer characteristics and b on-state drain current with L ov

Subsequently, the main device parameters (N p, T p, N s) influencing tunneling rate are studied. The variations of transfer characteristics with different pocket-doping concentrations (N p) are shown in Fig. 9a. The off-state drain current increases by four orders of magnitude when the N p increases from 1 × 1019/cm3 to 2 × 1019/cm3. This is because conduction band and valence band of tunneling junction closely align with each other in off-state when the N p is very high. As a result, 1 × 1019/cm3 is regard as the optimal N p because it obtains not only higher on-state current but also lower off-state current. The pocket thickness (T p) also has influence on the performance of HTG-TFET on condition that other parameters remain constant. Figure 9b shows that off-state current increases with increasing T p. When T p is large, the wider depletion region leads the pocket to be partially depleted, resulting in an increased electron concentration between the source and the pocket regions. The subthreshold conduction is now determined by the carrier diffusion instead of the BTBT. Besides, the source-doping concentration (N s) has the similar influence on the device performance. From Fig. 10, it can be obviously observed that the lower N s and higher N s have the bad effects on on-state current and off-state current, respectively. When the N s is 2 × 1020/cm3, the valence band pulled up significantly in the source region leads to the smaller tunneling distance at off-state, which can be seen in Fig. 10b. When the N s is 5 × 1019/cm3, there is a very large tunneling distance at on-state, which diminishes electron BTBT rates, as shown in Fig. 10c. In conclusion, the optimal N p, T p, and N s are chosen as 1 × 1019/cm3, 5 nm, and 1 × 1020/cm3, respectively.

Fig. 9
Variations of transfer characteristics with different a N p and b T p
Fig. 10
Influences of N s on a transfer characteristics, b off-state energy band, and c on-state energy band

Finally, the capacitance characteristics of HTG-TFET, LG-TFET, and UTFET are also investigated by using an AC small signal simulation with the operating frequency of 1 MHz. In the TFETs, due to the presence of source-side tunneling barrier, the gate-to-source capacitance (C gs) is very small. Therefore, the Miller capacitance mainly depends on the gate-to-drain capacitance (C gd) [19, 20].

Figure 11 shows the capacitance-voltage characteristics of the HTG-TFET, UTFET, and LG-TFET. From Fig. 11a, it can be seen that C gs of HTG-TFET is larger than that of UTFET and LG-TFET. This is due to the larger overlap of C gs in HTG-TFET. The inversion layer is formed from the drain region and is expanded into the source region by increasing gate voltage, which screens the source-side inner-fringe capacitance to reduce C gs. However, when the gate voltage is larger than 0.7 V, the elimination of inner-fringe capacitance makes the barrier capacitance across tunneling junction be dominated component of C gs. Therefore, C gs of these three devices increases with increasing gate voltage. In these three devices, the increasing of C gd with the increasing gate voltage, as shown in Fig. 11b, is mainly caused by depletion capacitance at drain side. In the HTG-TFET, although the drain is placed at the bottom of gate, the light doping channel separates the gate oxide and drain region. As a result, the C gd corresponds to series capacitances of overlap capacitance and depletion capacitance, which is helpful for the suppression of C gd. Due to the decreased C gd, this design cannot cause severe Miller capacitance problem for circuit design.

Fig. 11
Capacitance-voltage characteristics of the HTG-TFET, UTFET, and LG-TFET at V d = 0.5


In this paper, a novel heterojunction TFET with a T-shaped gate (HTG-TFET) is proposed and its advantages over other counterparts are studied using Silvaco-Atlas simulation. Due to the overlap of gate and pocket in both the vertical and the lateral directions, the tunneling area and electric field at the top of tunneling junction are enhanced so that on-state drain current increase obviously. Moreover, the heterojunctions formed between silicon source and SiGe pocket regions help device to obtain better performance. Although dual sources in HTG-TFET increase C gs, the reduced C gd cannot bring sever Miller capacitance. The parameters that affect the performance of HTG-TFET, including L ov, N p, T p, and N s, are also investigated by simulations. On the premise that optimal parameters are used in simulations, the HTG-TFET obtains the optimum performance that on-state current is 7.02A/μm, average SS is 44.64 mV/dec, and point SS is 36.59 mV/dec at V g = 0.2 V. Therefore, HTG-TFET can be a potential candidate for the next generation of low-power electron device.


We acknowledge the Project of National Natural Science Foundation of China and the valuable suggestions from the peer reviewers.


The role of the Project of National Natural Science Foundation of China (61504100) is designing the work; the role the Project of National Natural Science Foundation of China (61434007) is the collection, analysis, and interpretation of the data.

Authors’ Contributions

WL generated the research idea, analyzed the data, and wrote the paper. WL and SpC carried out the simulation. WL, SpC, and ZnY participated in the discussion. SlW and HxL have given the final approval of the version to be published. All authors read and approved the final manuscript.

Authors’ Information

WL and SpC are Ph.D students in Xidian University. SlW is a doctor in Xidian University. HxL is a professor in Xidian University. ZnY is a doctor in Xi’an University of Technology.

Competing Interests

The authors declare that they have no competing interests.


Publisher’s Note

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Contributor Information

Hongxia Liu, moc.ude.naidix.liam@uilxh.

Shulong Wang, nc.ude.naidix@gnawls.


1. Wang PF, Hilsenbeck K, Nirschl T, Oswald M, Stepper C, Weis M, et al. Complementary tunneling transistor for low power application. Solid State Electron. 2004;48(12):2281–2286. doi: 10.1016/j.sse.2004.04.006. [Cross Ref]
2. Seabaugh AC, Zhang Q. Low-voltage tunnel transistors for beyond CMOS logic. Proc IEEE. 2010;98(12):2095–2110. doi: 10.1109/JPROC.2010.2070470. [Cross Ref]
3. Villalon A, Carval GL, Martinie S, Royer CL, Jaud MA, Cristoloveanu S. Further insights in TFET operation. IEEE Trans Electron Devices. 2014;61(8):2893–2898. doi: 10.1109/TED.2014.2325600. [Cross Ref]
4. Choi WY, Park BG, Lee JD, Liu TJK. Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) Less than 60 mV/dec. IEEE Electron Device Lett. 2007;28(8):743–745. doi: 10.1109/LED.2007.901273. [Cross Ref]
5. Ganapathi K, Alahuddin S. Heterojunction vertical band-to-band tunneling transistors for steep subthreshold swing and high on current. IEEE Electron Device Lett. 2011;32(5):689–691. doi: 10.1109/LED.2011.2112753. [Cross Ref]
6. Wang P, Tsui B. Band engineering to improve average subthreshold swing by uppressing low electric field band-to-band tunneling with epitaxial tunnel layer funnel FET structure. IEEE Trans Nanotechnol. 2016;15(1):74–79. doi: 10.1109/TNANO.2015.2501829. [Cross Ref]
7. Kim SW, Choi WY, Sun MC, Kim HW, Park BG. Design guideline of Si-based L-shaped tunneling field-effect transistors. Jpn J Appl Phys. 2012;51(6S):06FE09-1–06FE09-4.
8. Kim SW, Kim JH, Liu TJK, Choi WY, Park BG. Demonstration of L-shaped tunnel field-effect transistors. IEEE Trans Electron Devices. 2016;63(4):1774–1778. doi: 10.1109/TED.2015.2472496. [Cross Ref]
9. Wang W, Wang PF, Zhang CM, Lin X, Liu XY, Sun QQ, et al. Design of U-shape channel tunnel FETs with SiGe source regions. IEEE Trans Electron Devices. 2014;61(1):193–197. doi: 10.1109/TED.2013.2289075. [Cross Ref]
10. Yang ZN. Tunnel field-effect transistor with an L-shaped gate. IEEE Electron Device Lett. 2016;37(7):839–842. doi: 10.1109/LED.2016.2574821. [Cross Ref]
11. Singh G, Amin SI, Anand S, Sarin RK. Design of Si0.5Ge0.5 based tunnel field effect transistor and its performance evaluation. Superlattice Microstruct. 2016;92:143–156. doi: 10.1016/j.spmi.2016.02.027. [Cross Ref]
12. Asthana PK, Ghosh B, Goswami Y, Tripathi BMM. High-speed and low-power ultradeep-submicrometer III–V heterojunctionless tunnel field-effect transistor. IEEE Trans Electron Devices. 2014;61(2):479–486. doi: 10.1109/TED.2013.2295238. [Cross Ref]
13. Kao KH, Verhulst AS, Vandenberghe WG, Sorée B, Magnus W, Leonelli D, et al. Optimization of gate-on-source-only tunnel fets with counter-doped pockets. IEEE Trans Electron Devices. 2012;69(8):2070–2077. doi: 10.1109/TED.2012.2200489. [Cross Ref]
14. Mallik A, Chattopadhyay A, Guin S, Karmakar A. Impact of a spacer–drain overlap on the characteristics of a silicon tunnel field-effect transistor based on vertical tunneling. IEEE Trans Electron Devices. 2013;60(3):935–943. doi: 10.1109/TED.2013.2237776. [Cross Ref]
15. Kim HW, Kim JH, Kim SW, Sun MC, Park E, Park BG. Tunneling field-effect transistor with Si/SiGe material for high current drivability. J Appl Phys. 2014;53(6S):06JE12-1–06JE12-4.
16. Vandooren A, Leonelli D, Rooyackers R, Hikavyy A, Devriendt K, Demand M, et al. Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction tunnel-FETs. Solid State Electron. 2013;83:50–55. doi: 10.1016/j.sse.2013.01.026. [Cross Ref]
17. SILVACO International, Santa Clara, CA 95054, USA, ATHENA/ATLAS User’s Manual (2012)
18. Choi WY, Lee HK. Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) Nano Convergence. 2016;3(13):1–15. [PMC free article] [PubMed]
19. Saurabh M, Ramakrishnan K, Suman D, Vijaykrishnan N. Effective capacitance and drive current for tunnel fet (TFET) CV/I estimation. IEEE Trans Electron Devices. 2009;56(9):2092–2098. doi: 10.1109/TED.2009.2026516. [Cross Ref]
20. Saurabh M, Ramakrishnan K, Suman D, Vijaykrishnan N. On enhanced Miller capacitance effect in interband tunnel transistors. IEEE Electron Device Lett. 2009;30(10):1102–1104. doi: 10.1109/LED.2009.2028907. [Cross Ref]

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