The TEM image in Figure b shows the rounded corners of the twin TFT device structure. First, the NW tri-gated structure, formed by e-beam lithography, was dipped into DHF solution, forming rounded corners. Then, thermal oxidation was performed to form the tunneling oxide; the junction of the channel and the tunneling oxide exhibits some rounding, protecting the tunneling oxide against excessive damage when it is written and erased. The P/E speed and reliability are balanced by Ω-gate formation. By technology computer-aided design (TCAD) simulation, Figure shows the electric field of NWs using tri-gate and Ω-gate structures. The result indicates that the Ω-gate structure has more programming sites around the NWs than the tri-gate structure which are only at the upper corners and that the Ω-gate structure also has smoother electric field.
Electric field of NWs. By TCAD simulation, cut from the AA’ line in the (a) schematic, the electric field around the NWs of (b) tri-gate and (c) Ω-gate structures is shown.
Figure compares the P/E speed of the BBHE operation with that of the FN operation. The device was programmed by FN injection at Vgs = 17 V and by BBHE injection at Vgs = 7 V with Vds = −10 V. The BBHE operation exhibits higher programming speed than the FN operation.
Programming and erasing characteristics of the EEPROM cell with devices. The P/E speed of BBHE operation is compared with that of FN operation.
Figure a shows the twin poly-Si TFT-based (Weff
= 113 nm × 10/6 μm/10 μm) EEPROM P/E cycling endurance characteristics by FN and BBHE, respectively, using the same input voltage. As the number of P/E cycles increased, the magnitude of the memory window disappeared. The floating-gate memory device maintained a wide threshold voltage window of 3.5 V (72.2%) after 104
P/E cycles for FN operation. For BBHE operation, the memory window was almost closed after 104
P/E cycles. Figure b shows high-temperature (85°C) retention characteristics of NW-based (Weff
= 113 nm × 10/6 μm/10 μm) EEPROMs. This figure reveals that after 10 years, the memory window was still 2.2 V when using FN operation. For BBHE operation, the device exhibited almost no data retention capacity. The Ω-gate structure has a higher P/E efficiency than the tri-gate structure because the four corners of the channel are all surrounded by the gate structure [13
]. The Ω-gate structure contributes to the equal sharing of the electric field and reduces the probability of leakage in the floating-gate devices in the form of stress-induced leakage current, improving the reliability of the device. Also, the extra corners improve the P/E speed.
Endurance and retention characteristics. (a) Endurance characteristics of the twin poly-Si TFT EEPROM by FN and BBHE. (b) Retention characteristics of the twin poly-Si TFT EEPROM at 85°C by FN and BBHE.
Figure displays a TCAD simulation of FN and BBHE operations. The result indicates that the FN operation produces a high average electric field in the tunneling oxide from the source to the drain, programmed by the tunneling effect. FN operation indicates the average wearing of electric field on the tunneling oxide. BBHE operation produces a sudden electric field peak at the source side, programmed using hot electrons with high energy, causing considerable local damage to the tunneling oxide. This result of consistent P/E that is caused by FN operation reveals better endurance and retention than the BBHE operation for floating-gate devices.
TCAD simulation. (a) FN programming. VFG = VCG × αG = 14.9 V. (b) BBHE programming. VFG = VCG × αG = 5.95 V. Both use the same voltage drop. (c) Electric field comparison of FN and BBHE programming.