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The development of a robust method for integrating high-performance semiconductors on flexible plastics could enable exciting avenues in fundamental research and novel applications. One area of vital relevance is chemical and biological sensing, which if implemented on biocompatible substrates, could yield breakthroughs in implantable or wearable monitoring systems. Semiconducting nanowires (and nanotubes) are particularly sensitive chemical sensors because of their high surface-to-volume ratios. Here, we present a scalable and parallel process for transferring hundreds of pre-aligned silicon nanowires onto plastic to yield highly ordered films for low-power sensor chips. The nanowires are excellent field-effect transistors, and, as sensors, exhibit parts-per-billion sensitivity to NO2, a hazardous pollutant. We also use SiO2 surface chemistries to construct a ‘nano-electronic nose’ library, which can distinguish acetone and hexane vapours via distributed responses. The excellent sensing performance coupled with bendable plastic could open up opportunities in portable, wearable or even implantable sensors.
The fabrication of electronic devices on plastic substrates has attracted considerable recent attention owing to the proliferation of handheld, portable consumer electronics. Plastic substrates possess many attractive properties including biocompatibility, flexibility, light weight, shock resistance, softness and transparency1–3. However, most plastics deform or melt at temperatures of only 100−200 °C, placing severe limitations on the quality of semiconductors that can be grown directly on plastic. Central to continued advances in high-performance plastic electronics is the development of robust methods for overcoming this temperature restriction. Recently, three categories of approaches have emerged to address this problem.
The first approaches are crystallization methods, in which an inferior inorganic semiconductor is vapour deposited at low temperatures onto plastic, and subsequently crystallized. An example is the conversion of amorphous silicon into polycrystalline silicon via laser crystallization4. Polysilicon thin-film transistors (TFTs) made in this way have yielded electron mobilities up to 250 cm2 V−1 s−1 and hole mobilities up to 65 cm2 V−1 s−1 (refs 5–7). However, this approach suffers from an inherent dichotomy between achieving high performance, which requires larger crystal grain sizes, and achieving homogeneity, which requires smaller grain sizes for uniformity in number of grain boundaries per device2,4,8. Second are wet-transfer, or ‘bottom-up’, methods. Single-crystalline materials are prepared at high temperatures, and cast from solution onto plastic at ambient temperatures9–13. Silicon nanowire (Si NW)-based high-mobility transistors9,11 and high-frequency ring oscillators10 have been made using this approach. However, achieving spatially specific, highly ordered nanowire films from solution remains a prominent challenge, although impressive progress has been made using Langmuir–Blodgett techniques14,15. The third category of techniques are dry-transfer methods involving the relocation of semiconductor materials16 or fully fabricated devices17 from inorganic substrates to plastic using poly(dimethylsiloxane) (PDMS) stamps or soluble glues. Dry transfer has been used to print a variety of photolithographically defined semiconductor microwires16,18–20 onto plastic. These microstructured ribbons21 are useful for circuits where high currents are required.
The dry-transfer method is particularly interesting where highly ordered structures are involved because, in principle, morphology is preserved by the transfer procedure. Yet, to date, achieving highly ordered, high-performance nanowire electronic circuits on plastic substrates has not been demonstrated. We previously reported on the superlattice nanowire pattern transfer (SNAP) approach for achieving highly regular arrays of metal and semiconductor nanowires22. Extremely high control over nanowire width, length and pitch results from the translation of atomically precise epitaxial superlattice layers into a similar level of control over NW width and spacing. SNAP Si nanowires have been shown to possess hole mobilities as high as 100 cm2 V−1 s−1, a value comparable to the mobility of bulk Si at similar dopant densities23,24. Here, we show that SNAP NW arrays can be transferred onto plastic substrates using a simple, parallel and scalable transfer process under ambient conditions19. Nanowire organization is retained over large areas, and the printed nanowires yield excellent performance as both field-effect transistors (FETs) and as vapour sensors.
The dry transfer process uses the fact that the SNAP procedure is carried out on silicon-on-oxide (SOI) wafers, as the buried silica can be readily etched to free the wires for transfer. Figure 1 summarizes the procedure. First, Si NWs were fabricated from an SOI wafer, which was doped with p-type spin-on dopants23 (see the Methods section), yielding a doping level of ~1018 cm−3. Arrays of Si NWs were defined by imprinting a Pt-coated cleaved edge of a GaAs/AlxGa1−xAs (34 nm/17 nm) superlattice wafer grown by molecular beam epitaxy into the SOI film (see the Methods section). The Pt wire arrays are used as protective masks for translating the ordered geometry into the single-crystal silicon via anisotropic etching. The buried oxide of the SOI wafer acts simultaneously as an etch stop and electrically isolates the NWs. The resulting NW arrays consisted of 400 high-aspect-ratio (>105) 18-nm-wide Si NWs at a centre-to-centre pitch of 51 nm (Fig. 1a).
Next, the buried oxide—exposed after SNAP fabrication—was isotropically etched in concentrated HF to loosen the NWs from the host wafer without completely dislocating them (see the Methods section). A fresh piece of PDMS was brought into conformal contact with the wafer and quickly peeled back to retrieve the ordered NW arrays (Fig. 1b,c). Optical and scanning electron microscope (SEM) images of the PDMS surface (not shown) confirm that the entire SNAP NW array is cleanly and efficiently freed from the host wafer while larger residual blocks of silicon are left behind. Separately, a plastic sheet (mylar) pre-coated with indium tin oxide (ITO) was washed thoroughly and spin-cast with a 2 µm layer of SU-8 epoxy (Fig. 1d). The transfer process is effected by (1) bringing the surface of the PDMS containing the SNAP wires into conformal contact with the epoxy layer on the plastic, (2) curing the epoxy by heat and exposure to ultraviolet light and (3) slowly peeling off the PDMS to release the NWs (Fig. 1e,f).
SEM images of the plastic substrate following the transfer printing reveal that the highly aligned structure of the SNAP Si NWs is not disturbed by the process (Fig. 2). At low magnifications, the entire SNAP film can be seen to remain largely intact and stretch over a length many times the wire diameters (up to several millimetres) (Fig. 2a). One edge of the film shows a small number of wandering wires, most likely due to shear forces from peeling the PDMS. Close inspection of the original SOI host wafer as well as the PDMS transfer piece show that only a few (<3%) of the SNAP wires are lost during the transfer steps. Because the transfer process is carried out entirely in parallel, the quantity and area of transferred nanowires depends solely on the initial quantity of SNAP wires taken from the host SOI substrate. Recent studies suggest that the SNAP process can be carried out at the wafer scale via successive imprinting steps to create a wafer-scale master for secondary compression moulding25.
Higher-magnification images reveal that the SNAP NWs stretch over many micrometres in length at close packing without any breakage or substantial bundling. High-resolution images reveal wire diameters of ~18 nm, which is close to the 17 nm thickness of the initial AlxGa1−xAs thin-film layer (Fig. 2b). The total width of the NW array (Fig. 2a) is about 16 µm. Assuming that 390–400 NWs were transferred, then the average pitch of the NW array is about 41 nm, which is slightly smaller than the 51 nm pitch of the original superlattice template. We attribute this ‘lateral compression’ in the film to the initial HF etching step, which removes SiO2 between the wires.
To fully characterize the electronic performance of the SNAP NW film on plastic, FETs were constructed from the film (Fig. 3a). Previous studies have shown that transistor performance correlates with the performance of related devices, such as sensors26. The devices were fabricated by coupling the SNAP-to-plastic process with conventional microfabrication techniques23 (Fig. 3; see the Methods section). After transferring SNAP NWs onto plastic, a contact metal layer of 1,000 Å Ti was uniformly evaporated across the entire plastic chip. This layer was subsequently patterned via photolithography and HF etching to form source/drain (S/D) finger electrodes across the SNAP wire array. The nanowire array was then sectioned into individual device islands with photolithography and etching. The resulting device channels were 5 µm in length. In this geometry, the ITO can be used as a voltage gate for the FETs, with the 2-µm-thick SU-8 as a gate dielectric. More efficient top-gate electrodes were also fabricated: a uniform dielectric layer of 250 Å SiO2 was deposited across the devices, on top of which Ti gates matched to the S/D gaps were patterned.
Figure 3b shows the transistor performance of a device containing about 200 wires. The two-terminal current versus source–drain voltage (IDS–VDS) curves (Fig. 3b, inset) are all linear through the origin, suggesting that the metal electrodes make ohmic contacts to the SNAP NW array. The curves also show clear saturation behaviour at larger negative biases, and the gate dependence of the curves confirms p-type NWs24. Figure 3b shows the transfer characteristics of the NW arrays. On-currents of these devices are as high as 10 µA, and can be scaled by varying the number of wires bridging the electrodes. The ITO gate shows poor modulation of the conductance owing to the large thickness of the SU-8 gate dielectric. In contrast, the top gate shows up to 105 order of magnitude changes in channel conductance (hysteresis is 1.5 V of the 10 V sweep range), with a subthreshold swing of only 300 mV per decade. This low-subthreshold slope is comparable to the best p-type polysilicon TFTs on plastic17 and an indicator of low-power operation. This point of low power is corroborated by the fact that all devices tested were enhancement-mode devices, requiring a small negative applied gate voltage to turn on; this threshold voltage was in the range of −2 to 3V for all devices measured.
Finally, the transconductance of the top-gated device is 5 µS, determined from the maximum absolute slope of the IDS versus VGS curve when plotted on a linear scale (not shown). This value is approximately one order of magnitude smaller per NW when compared with the best performance of SNAP wires on their native substrates23. This may simply arise from the poor quality of the electron-beam deposited SiO2 dielectric, but it could also result from the inability of the plastic to withstand high-temperature annealing of the contacts, which is crucial for ensuring efficient contact to all wires in the arrays and for minimizing charge traps and defects23,24,27,28. We are currently investigating alternative approaches to further optimize device performance, including the use of high-κ dielectrics29,30.
Our ability to prepare low-power, high-response nanoscale semiconductors on plastic enabled us to explore the development of biological or chemical sensors on plastic. The advantage of such sensors include their increased portability and their potential use as implants31–33. Several investigators have demonstrated nanowire and nanotube devices for high-performance chemical and biomolecular sensing26,34–40.Multiple-nanowire/tube films were especially sensitive owing to the cumulative response of the wires as well as the low-noise profile resulting from multidevice averaging35,36. For sensing purposes, SNAP nanowires have several advantages. First, they allow for the precise control over dopant type and concentration23. In addition, Si NW surfaces have a well-established chemistry26,27,37, thus allowing for the ready chemical modification of NW sensors for increasing the selectivity and diversity of an NW sensing array.
As a demonstration, we fabricated sorption-based vapour sensor arrays from the NW-on-plastic films (Fig. 4). The plastic chips (Fig. 4a, inset) were wire-bonded to a chip carrier and placed in a home-built gas delivery chamber equipped with electrical feed-throughs. First, to determine the ultimate sensitivity resolution capabilities of the sensor arrays, we used a flow-through technique to sequentially measure the response to NO2 gas diluted in N2. NO2 is one of the most dangerous environmental pollutants, primarily produced from internal-combustion-engine emissions. The national air quality standard for mean annual NO2 exposure is 53 p.p.b., and concentrations above this level may cause increased smog, acid rain and respiratory problems in children with asthma41.
Figure 4b shows the normalized response of an NW sensing element to order-of-magnitude changes in NO2 concentration. The initial resistance, R0, is taken under pure flowing N2. On exposure to 20 p.p.m. NO2, the device exhibits a ~3,000% current increase after only 1.25 min. We attribute this large increase in current (increase in −ΔR) to the strong electron-withdrawing capabilities of NO2, which have the equivalent effect of hole carrier injections into the p-type Si NWs. This response was reversible and the device was refreshed via repeated cycles of vacuum pumping and flushing with air. Gentle heating of the sensor device would be expected to accelerate this recovery process, but was not necessary for the experiments reported here. The device can detect concentrations down to at least 20 p.p.b. of NO2: the sensor registers a substantial 10% current increase after 15 min of exposure to 20 p.p.b. (Fig. 4b, inset). This response is significantly larger than the <1% drift in current for the 10 min before gas delivery. This sensitivity metric is less than half the 53 p.p.b. national requirement standard41, and is comparable to sensors fabricated from as-grown nanotubes (10–50 p.p.b.) (refs 34,35) and metal-oxide nanowires (5–20 p.p.b.) (ref. 36) on conventional Si substrates. Furthermore, these flexible sensors are 100-fold more sensitive than thin-film metal-oxide sensors42,43. We attribute this exquisite sensitivity to the fact that binding events occur near the top surface of the NWs, where most of the charge carriers reside. Indeed, for SNAP Si NWs, the majority of the dopants reside in the top 10 nm of the wires44. Theoretical studies are also underway to render the sensors fully quantitative (‘calibration-free’) via advanced modelling techniques26.
A large assortment of commercially available reagents for modifying the SiO2 surface of the NWs is available; depending on the reaction conditions, these silanes can even provide coverage at the level of a single molecular monolayer45. We used several such silanes to fabricate a sensor library on plastic (Fig. 5). This ‘nanoelectronic nose’ consists of an integrated set of four sensors broadly functionalized to impart a reversible fingerprint pattern of response for a given gas46–48. The sensing elements were chemically modified by flowing alkane-, aldehyde- and amino-silanes through PDMS microfluidic chambers aligned to the plastic chip (see the Methods section). A fourth sensing element was left unmodified. Following literature protocols48,49, we measured the response of the NW sensor library to 1,000 p.p.m. of acetone and hexane vapours (Fig. 5a). The individual chemiresistors clearly respond differently to each gas, and furthermore the collection of sensors responds differently to the two gases. All of the elements increase in conductance relative to their baseline values, but the NW surface chemistry determines the magnitude of the response. We are undertaking experimental and theoretical investigations into the mechanism of these responses, which may result simply from vapour–wire dipole–dipole effects, but could also involve dehydration of the surface, displacement of adsorbed oxygen and/or changes in surface-charge screening.
The bar plot of Fig. 5b summarizes the sensing response of the library to the two gases. The height of each bar represents the percentage change in conductance following 5 min of vapour exposure. By normalizing the signal of each sensing element to its maximum value of response, the overall fingerprint pattern of the response can be visualized as a radial plot (Fig. 5b, inset). Each axis of the plot corresponds to the four different surface functionalities, and the connected points of the axes graphically represent the ‘image’ of the gas. The visual distinction between acetone and hexane is immediately apparent. A simple correlation analysis was used to quantify this difference; processing the data in this way yields a correlation coefficient of about 0.5 for the nanostructure array responses to acetone and hexane46,49. For a population of four sensors, this correlation is statistically weak. Therefore, although no individual element shows specificity for the solvent gases, discrimination by the nano-nose is achieved via the collective response patterns48. The correlation value can be further decreased by including more sensing elements in the library or by increasing the selectivity of individual elements for specific gases. We are currently exploring chemical and theoretical approaches towards improving this nanowire nose by amplifying its selectivity to a host of toxic and non-toxic gases, including molecular disease indicators in the breath50.
In summary, ordered arrays of doped silicon nanowires can be comprehensively transferred to flexible plastic substrates using conditions that retain the highly regular morphology of the nanowire arrays. FETs fabricated from the transferred wires using standard microprocessing techniques yield large on/off ratios and low-power operation. Sensor arrays on bendable plastic exhibited sensitivities comparable to the best nanotube and metal-oxide nanowire devices on Si substrates. A ‘nanoelectronic nose’ prepared by chemically functionalizing individual elements within an array of sensors demonstrated the capability to discriminate low concentrations of acetone and hexane solvent vapours via an analytical mapping of the array response patterns. These results may have implications in the use of sensors for applications that range from real-time pollution regulation to highly portable biological- and chemical-threat detectors. Furthermore, the low power/heat dissipation and high sensitivity of these devices coupled with the inherent biocompability of the plastic substrates may have exciting applications in continuous in vivo biomolecular monitoring.
Silicon nanowires were fabricated from an intrinsic, 320-Å-thick SOI film (100 orientation) (Simgui) with a 2,500 Å buried oxide. After thorough cleaning and rinsing with de-ionized water, the substrate was coated with p-type spin-on dopants (Boron A, Filmtronics). Dopants were diffused into the SOI film using rapid thermal processing at 800 °C for 3 min. Four-point resistivity measurements, correlated with tabulated values, yielded a doping level of ~1018 cm−3. Separately, a superlattice consisting of 800 layers of alternating GaAs and AlxGa(1−x) As thin films was prepared (IQE). The superlattice was cleaved along a single crystallographic plane and thoroughly cleaned by sonicating in methanol and gentle swabbing. The exposed edge was immersed in NH3/H2O2/H2O (1:20:750 v/v) for 10 s to selectively etch the GaAs regions (etch depth ~30 nm). The resulting edge of the superlattice thus consisted of AlxGa(1−x) As plateaux separated by GaAs valleys. Pt metal was deposited using electron-beam evaporation onto the edge of the AlxGa(1−x) As ridges, with the edge of the superlattice held at a 45° angle to the incident flux of Pt atoms. The Pt-coated superlattice edge was then brought into contact with the doped SOI substrate spin-coated (6,000 r.p.m., 30 s) with a thin-film PMMA/epoxy (1:50 wt/wt). The superlattice/epoxy/SOI sandwich was dried on a hot plate (150 °C, 40 min), and the superlattice was released by a selective etch in H3PO4/H2O2/H2O (5:1:50 v/v, 4.5 h) solution, leaving a highly aligned array of 400 Pt NWs on the surface of the SOI substrate. These Pt NWs served as protective masks for a reactive ion etch process to produce aligned, single-crystal Si NWs (CF4/He, 20/30 s.c.c.m., 5 mtorr, 40 W, 3.5 min). The Pt NWs were dissolved in aqua regia (30 min) to produce an array of 400 Si NWs. Finally, the substrate was cleaned in ALEG-355 solution (Mallinckrodt Baker) to remove residual epoxy.
An as-prepared SNAP nanowire substrate was dipped in concentrated HF for 5 s. A slab of PDMS was brought into conformal contact with the top surface of the wafer and then quickly peeled back to retrieve the nanowire array. Separately, a 100-µm-thick sheet of poly(ethylene terephthalate) (PET; Mylar; CP Films) coated with 100-nm-thick ITO was washed with acetone, isopropanol and deionized (DI) water and dried with a stream of nitrogen. The ITO/plastic was treated to oxygen plasma activation (300 mtorr, 60W, 60 s) and spin-cast with the photoresist SU-8 2002 (Microchem) (3,000 r.p.m., 30 s). The photopolymer was pre-cured on a hot plate (65 °C, 1 min), at which point the PDMS containing the SNAP wires was allowed to achieve conformal contact with the warm epoxy. The hot plate was then ramped to 95 °C and the PDMS/mylar sandwich was baked for 5 min. The epoxy layer was cured by backside exposure to ultraviolet light through the PET sheet for 1 min. The PDMS was carefully peeled from the plastic, concluding transfer of the SNAP nanowire arrays onto plastic. To ensure complete cross-linking, the SU-8 was exposed to ultraviolet again for 1 min and hard-baked at 115 °C for 15 min.
The plastic chip containing the SNAP wire arrays was rinsed with DI water and then treated to mild O2 plasma (300 mtorr, 30W, 30 s). The chip was immersed in buffered oxide etch for 3 s to remove oxides and promote the formation of ohmic contacts. Source and drain electrodes were formed by electron-beam evaporating 1,000 Å Ti uniformly across the PET chip, and then patterning the Ti through a photoresist mask (Shipley 1813) via wet etching (1:1:10 HF/H2O2/DI v/v, 5 s). The resulting device channels were 5 µm in length. A new photoresist mask was applied to expose unwanted regions of the NW array for sectioning into device islands. The Si was removed via reactive ion etching (SF6, 20 s.c.c.m., 20 mtorr, 30W, 1 min) and the photoresist was removed in acetone. At this stage, the chip could be used for sensing experiments. For FETs, the chip was processed further by uniformly electron-beam evaporating 250 Å SiO2 as a gate dielectric. A photoresist mask was applied on top of the silica to define a top-gate geometry, through which 500 Å Ti was deposited and lifted off in acetone.
A silicon wafer (Virginia Semiconductor) was thoroughly cleaned in acetone and isopropanol and spin-coated with SU-8 2015 (1,750 r.p.m., 30 s) (Microchem). The photoresist was baked at 65 °C for 2 min and 95 °C for 4 min, and then exposed to a microfluidic channel pattern by conventional photolithography. The resist was post-baked at 65 °C for 1 min and 95 °C for 8 min, developed for 4 min in SU-8 developer (Michrochem), rinsed with isopropanol and hard-baked at 180 °C for 15 min. The SU-8-patterned wafer was then coated with PDMS prepolymer and cured. A plastic chip fabricated with Si NW sensor arrays was treated to a plasma oxidation step (O2, 300 mtorr, 30W, 60 s) and a PDMS stamp containing microfluidic channels was aligned to the plastic such that the channels intersected with the sensors. Surface modification reagents consisting of 1% ethanol solutions of a variety of silanes (n-octyltriethoxysilane, 3-aminopropyltrimethoxysilane, trimethoxypropylsilane aldehyde) (United Chemical Technologies) were injected into the channels and allowed to react for 45 min. The PDMS channel was removed, the plastic chip was rinsed thoroughly with isopropanol, and heated at 110 °C for 15 min.
Electrical characterization of FETs was carried out on a standard probe station equipped with d.c. Cu–Be probes (Miller Design & Equipment). Two source-measure units (Keithley Instruments 2400) controlled by a general purpose interface bus computer port were used to bias the devices and read out current. Custom-programmed computer software (National Instruments LabVIEW) was used to collect data. Electrical characterization of sensors was achieved with a pre-amplifier (Stanford Research Systems) interfaced to a data acquisition card and BNC adapter breakout panel (National Instruments). Data was collected with a custom-programmed software routine (National Instruments LabVIEW). The plastic sensor chips were wire-bonded to a chip carrier and placed in a home-built gas delivery chamber with electrical feed-through. Acetone, hexane and NO2 vapours (Matheson Tri-Gas) were introduced at a flow rate of 30–300 s.c.c.m., and, if necessary, diluted in N2 at a flow rate of 800–1,000 s.c.c.m.
We thank W. Dichtel, A. Boukai and Y. Bunimovich for useful discussions. M.C.M. thanks the Intelligence Community Postdoctoral Research Fellowship Program for financial support. J.R.H. acknowledges primary support of this work via a contract from the MITRE Corporation, and support from the National Cancer Institute (#5U54 CA119347).
Author contributionsM.C.M. and J.R.H. conceived the experiments, M.C.M. carried out the experiments and M.C.M., H.A. and D.W. designed the experiments.
Competing financial interests
The authors declare no competing financial interests.