Integrated circuit design
The amplifier was a custom integrated circuit implemented using a commercial IBM 0.13-μm bulk CMOS mixed-signal process. The chip was designed and simulated using the Cadence Virtuoso software package.
The amplifier die was wirebonded to a 272-pin ball-grid array (BGA) package. Dam-and-fill doughnut epoxy encapsulation (Hysol FP4451 dam and FP4650 fill) covered the exposed gold wirebonds, leaving the die surface exposed.
By default, the amplifier chip surface had ~6-μm-thick passivation above the top metal interconnect layer. To reduce capacitive coupling to the electrolyte, after doughnut encapsulation the chip surface was passivated with the epoxy-based photoresist SU-8. Under yellow light, a drop of SU-8 2015 (Microchem) was manually applied to the surface of the amplifier die, filling the 300 μm-deep cavity formed by the epoxy dam. A light vacuum was applied in a dessicator for 15 min, followed by an overnight prebake in an oven at 80 °C. The chip was exposed in an MJB-3 UV contact aligner using a chrome-on-glass mask, 2,000 mW cm−2 dose, and 360 nm long-pass UV filter (Omega Optical). A post-exposure-bake for 30 min at 50 °C and development in SU-8 Developer (Microchem) yielded a layer of SU-8 ~200–300 μm thick with 300 μm × 300 μm square openings surrounding the 100 μm × 100 μm electrodes.
A watertight fluid chamber was constructed by fastening a 1 cm segment from a polypropylene tube to the top of the BGA package using polydimethylsiloxane (PDMS; Sylgard 184, Dow Corning).
After packaging the die, the aluminum was etched from the exposed surface electrodes by pipetting 500 μl of aluminum etchant (type A, Transene) into the fluid chamber for several minutes, followed by multiple rinses with deionized water.
The chip was mounted on a circuit board, powered on, and digital logic was applied to short-circuit the amplifier feedback element CF, clamping multiple channels’ electrodes at a constant voltage and providing a path for them to sink several micro-amperes of current. A small volume (~1 ml) of silver electroplating solution containing potassium silver cyanide (Transene), was added to the fluid chamber, and a silver wire counterelectrode was attached to a Keithley 2400 I–V meter and placed in the solution. The voltage was adjusted to achieve a counterelectrode current of 1 μA for several minutes, resulting in a deposition of ~10 μm of silver onto each electrode. After electroplating, the chamber was rinsed multiple times with deionized water.
The silver microelectrodes were converted to Ag/AgCl pseudo-reference electrodes by applying a drop of 10 μl 50 mM FeCl3
to the surface for 30 s (ref. 32
). After several hours of experiments, the chlorination typically needed to be repeated. We found that the chlorination could be repeated several times before the silver electrode was exhausted.
Nanopores in ultrathin silicon nitride membranes were fabricated in a similar manner as described else-where7
. Briefly, a 500-μm-thick silicon wafer with <100> crystal orientation (in which the <> notation refers to a material’s three-dimensional crystal orientation) and 5 μm of thermal oxide was coated with 25 nm of low-stress chemical vapor deposition silicon nitride (SiN). Standard UV photolithography was used to pattern square openings on one side of the wafer, through which the nitride and oxide were etched using SF6
plasma. The photoresist was stripped, and an anisotropic KOH etch followed by removal of the oxide layer resulted in ~50 μm × 50 μm free-standing windows on the reverse side of the wafer.
A film of poly-(methyl methacrylate) (PMMA, Microchem) was spun onto the membrane side of the window, and electron-beam lithography was used to pattern a small square opening of 500 nm × 500 nm or smaller. A SF6 plasma etch locally thinned the SiN in this region to ~10–15 nm. The confined area of this ultrathin region helped to limit the capacitance of the membrane and maintain its mechanical integrity. The PMMA was removed by incubation in acetone. A single nanopore was drilled through the thinned region of the nitride membrane using a JEOL 2010F HR-TEM. Fabricated pores were 2–6 nm in diameter, but the best signals from duplex DNA were obtained for 3.5–4 nm pores.
The nanopore chip was cleaned in piranha acid using a procedure described previously33
. After rinsing and drying the membrane, it was immediately mounted onto a custom Teflon fluid cell using KWIK-CAST silicone elastomer (World Precision Instruments). The silicone was carefully painted over the majority of the membrane-facing side of the chip, leaving an exposed <1 mm2
area around the membrane (). Additionally, for these experiments, silicone was applied on the amplifier chip surface, leaving only one preamplifier channel exposed.
When testing with the Axopatch 200B, the Teflon cell was placed into a mating fluid cell containing 1 M KCl 10 mM Tris buffer, pH 8.0. Inside a Faraday cage, two homemade Ag/AgCl pellet electrodes were connected to the headstage input and ground, respectively.
For testing with the CNP amplifier, the circuit board was placed in a small grounded aluminum box and the lower (trans) reservoir was filled with 500 μl 1M KCl, pH 8.0. The upper (cis) chamber in the Teflon cell was filled with 200 μl electrolyte, and the cell was placed into the amplifier chamber. An Ag/AgCl pellet electrode was placed in the cis chamber. The amplifier input voltage was held constant, as the potential of the opposing electrode was varied to apply a bias across the nanopore.
Supporting electronics and user interface
The preamplifier with its attached fluid chamber was mounted in a compression-mount BGA socket (Emulation Technologies) on a 15 cm × 13 cm circuit board and placed in a small aluminum box. The circuit board contained power regulation, biasing circuitry, analog signal buffering and filters, all of which were carefully designed for low-noise operation. The digital inputs to this board were galvanically isolated, and its outputs were fully differential. The board was powered from four AAA batteries and drew 30 mA. A second interface board outside the aluminum box hosted digital isolators, antialiasing filters (4-pole differential Bessel filter, fc = 1 MHz) and data converters (operating between 2–4 MS s−1), as well as an FPGA module (Opal Kelly XEM3010) with a 32 MB hardware data buffer and a high-speed USB interface. The data acquisition and control of the system were managed in real time through a custom graphical interface written in Matlab (MathWorks).
The data were processed using custom Matlab software. Traces were generally digitally filtered with a 128- or 512-tap finite-impulse-response low-pass filter to a desired signal bandwidth while retaining the 2–4 MS s−1 sample rate. Events were typically identified with a two-state thresholding algorithm in Matlab, but for traces with low SNR, a modified algorithm was used to identify the events: First, samples were identified whose values were more than 5 s.d. below the mean open pore current. Next, a local search found the nearest sample points at which the signal was above the open pore current. Finally, event edge times were assigned at the first and last points in these bounds that the signal was more than 4 s.d. from the baseline current.