The electrical characterization of the transistor was characterized by semiconductor parameter analyzer (Lakeshore, Desert Cryogenics Agilent HP 4156
C, Agilent Technologies, Santa Clara, CA, USA). Figure shows the transfer characteristic for DG and SGJLT. The pinch off effect can be seen due to positive lateral gate applying on the channel. The subthreshold swing (SS) and on/off ratio for double gate junctionless transistor (DGJLT) were 106
mV/decade, respectively, and for SGJLT were 105
mV/decade respectively. By increasing the positive gate voltage, the current dropped. This indicates that the device required positive gate voltage to be turned off. The pinch off effect for both devices is recognizable which off
state occurred in +1.5 and +2.5
V in DG and SG structures, respectively. The result for output characteristic shows that the drain current (ID
) does not significantly increase with the negative increase of gate voltage (not shown), unlike the conventional p-type channel metal-oxide-semiconductor field-effect transistor (MOSFETs). Also, high and positive threshold voltage (+1.2
V for SG and +0.8
V for DG) suggests that the device is in an on
state. It indicates that the transistor was in the on
state with zero gate voltage.
Transfer characterization graph for DG and SG JLT.
characteristics for SG and DG structures are shown in Figure for positive gate voltage. Low current is due to the low doping concentration profile (1015
) for the channel, which is lower than reported current value of the high doping concentration profile (5
) JLTs. The MOSFETs or JLTs with high doping concentration mostly suffered with the high scattering effect or threshold voltage variation. Low channel doping can improve field-effect mobility for improved transconductance and drive current and decrease the scattering effect and thresholdvoltage variations [38
]. It can also provide low current in an off
state; however, low off current is achievable by increasing the gate work function values. The electrical characteristics of the devices have the same trend compared to the reported cases fabricated by AFM nanolithography with nearly similar structure [21
]. In fact, in none of the reported cases, the devices were used as the pinch off device. Normally, high doping SOI was implemented and was never checked to use in a reverse bias to investigate the pinch off effect. Also in our work, we do not have remarkable increase in the current due to the negative gate voltage, while some previous works have shown a higher rate for increasing the current under the gate voltage (mostly positive voltage for the n-type case), and also a higher current value (due to the higher doping concentration).
Output characteristic (a) and drain conductance (b) for DG and SGJLT.
In Figure a, we can recognize the effect of the gate on channel in a DG structure which is more effective than SG due to the asymmetry of SG. In the DG structure the pinch off effect was achieved in VG
+2, while this value cannot provide the same current value in SG. This required higher voltage to approach pinch off effect in SG structure which was in VG
V (Figure ). Figure b shows the drain conductance for SG and DG structures under the different gate voltage. By increasing the gate voltage, the drain conductance for both structures will be decreased. For comparing DG structure to SG device, we have a more effective gate voltage in the channel approaching the pinch off effect (off
state) with lowest drain conductance, which is consistent to the output characteristics and our expectation about the DG structure. The trend for drain conductance is the same with MOSFETs [41
] and JLTs [42
], yet the slope is smaller here which can be explained by low doping concentration and current value.
In recent reports on experimental JLTs [18
], we did not encounter any case of on
state condition under the zero gate voltage due to having an opposite doping concentration for the gate and the channel, unless for the simulation cases and for very small gate lengths [48
]. The charge transmission in DG and SGJLT operates quite differently from the conventional MOSFETs and also slightly different from the JLT description in recent literature. The devices are working in on
state for nonzero VDS
V. The reason can arise from the fact that the field effects from the different work function of the gate and channel cannot cause the device to be turned off at VG
V due to the same doping concentration of the channel and gate contact, and no oxide layer for the gate.
Basically, regardless of the gate work function difference between the gate electrode and channel, JLTs are ‘gated resistor’ which is in the on
state at VG
]. According to the JLT’s principal, when the device is turned on, it approaches the flat band condition. It basically behaves as a resistor, and the electric field perpendicular to the current flow is equal to zero in the ‘bulk’ channel. In fact, as the advantage of our fabrication method, the AFM lithography keeps the surface and the body of the upper Si layer of the SOI intact and untouched. So we expect to find more bulk property, for example, higher mobility and less surface scattering effect for the channel under the gate.
Immediately after applying VSD
, the device goes to an on
state. The on
current is controlled by the semiconductor doping concentration and not by the gate capacitance. The operation of devices is outlined in Figure , and the three regions I, II, and III are denoted. The structures are a gated resistor turned off by depleting the channel (region II), when essential positive gate voltage is applied. It will be turned off based on the pinch off effect principle, when VG
provides a sufficiently large barrier in the gating region; the highest depletion occurs near to the drain side of the channel due to the stronger electric field in the drain side (Figure b,d). Figure a,c schematically show the devices in the on
state. In this condition, the subthreshold current flows by increasing the VDS
until the saturation current will be reached at region II, even for VG
V. Since the system is in on
state from VG
0, one can say that the threshold voltage is shifted into the positive voltage, and the neutral wire is instantaneously shaped when the bias is applied to the source/drain contacts (Figure a,c). That is the reason one can claim that the devices are already in flatband condition like the pinch off transistors [49
]. In the on
state condition, the holes concentration in the channel increases, and the neutral or undepleted channel forms between the source and the drain until the peak of the holes concentration in the channel reaches the doping concentration NA
Schematic operations (a,b) of the SG and DG (c,d) for positive and negative gate voltage.
In Figure , the schematic profile view of holes location transmission path and comparison of accumulation mode device with SG and DG device are shown. For the DGJLT the neutral wire locates in the center of the channel and close to the bottom, as shown in Figure , c and f. It is worth to mention that in SGJLT, the neutral or depleted wire will be formed not exactly in the center. Due to the specific shape of the device and having only one interface with BOX at the bottom, the neutral wire must be formed near to the bottom of the channel and away from the side gate sidewall (Figure , b and e). By further increasing the VDS
in the on
state, the depletion will be starting near to the drain due to high electric field in this area in region III, and this is the reason for having saturation for the current [51
]. The high electric field in the drain gives rise to the full depletion in nanowire near to the drain area acting as a buffer against the high electric field in the drain, which accordingly, will lead the current to be saturated.
Figure 8 Profile view of holes location transmission path in different devices (modified from).
However, by negatively raising the gate voltage, it is probable to have a little increasing of the current due to some accumulated charges, which were injected from the source (region I) to the channel (red color areas in Figure ). The drain current mainly flows through a bulk channel. An additional small conduction likely originated from a lightly accumulated channel in sidewalls facing the gates, when the gate voltage is large enough. The influence of the gate on the channel is not very effective to induce an accumulation mode due to the device configuration, low doping concentration, and the lack of oxide layer between the gate and the channel. Accordingly, increasing the gate voltage cannot help to make an effective accumulation layer and we do not expect to have the accumulation mode for high gate voltage. Normally in high doping JLTs in on
state, after increasing the gate voltage, the device is able to be converted into the accumulation mode with significant increasing of the current (mostly is not desired to reach) [9
]. Actually, another reason that we interpret the devices as JLT and not in accumulation mode is the ineffective negative increasing gate voltage on the channel.
In the accumulation mode, in on
state condition, the subthreshold current flows through the bulk of the device near the center of the nanowire just like the JLTs (Figure a). But the magnitude of this current is less than ten percent of the whole current achievable. By increasing the gate voltage, the majority of the holes are confined in inversion layers at the sidewalls, with marked peaks at the corners (Figure d). In the reported and high doping JLTs, we can increase the gate voltage in order to have accumulation charge and raise the current after reaching the flatband. But still, the largest part of the current is due to bulk conduction. The formation of a surface accumulation channel is also observed at high VG
. In comparison to the trigate FETs, Fin FETs, gate-all-around (GAA) FETs or reported JLTs in which there were more interfaces with the gate oxide layer or BOX and more current values after increasing the negative gate voltage for p-type channels. Here, we only have one interface between the channel and the BOX in order to provide charge accumulation. Accordingly, the increasing negative gate voltage is not able to produce more current compare to the trigate FETs, Fin FETs, GAA FETs, or reported JLTs. For our SG and DGJLTs as gated resistors, when the device is turned on, these essentially behave as a resistor, and the drain current is controlled by regions I and II and doping concentration. For linear region ID
could be given approximately by [47
is the semiconductor doping concentration, μ
is the effective mobility, q
is the electron charge; T
, and L
are the thickness, width, and the length of the channel respectively. Equation 1 was first time suggested by Colinge [9
] for JLTs and also by Fonash et al. [52
] who also suggested the similar equation before Colinge’s group about the accumulation mode of unipolar Si nanowire transistors. This equation points out that ID
is controlled by the doping concentration NA
, and not by the gate capacitance per area C. We believe that the ID
equation in our case would be very similar to Equation 1. For high doping concentration cases, which were mostly considered in literatures for JLTs, Equation 1 is suggesting for linear region. In our case, considering the on
state device, low concentration profile for the p-type material, and also the effect of the fins at the side of the channel to the source and the drain contacts, we suggest the same equation, unless, for the VDS
we have effective voltage for the channel VCh
, which is obeying the
. Then, we have
In the on state condition, for a given VDS, the electric field from the source to the negatively biased drain must be significantly small (nearly zero) in the neutral wire at the center of the channel. In the linear region we expect that the negative charge in region I (Figure ), which is adjacent to the area of I/II interface, should be gathered. This charge in the p-type material can only come from depletion in the channel in linear region.
In our case to enter the saturation region from linear region and since the device is trying to reach the saturation condition, we propose that we would have the condition at which the effective channel voltage become fixed at VChSat
. Then, further increases in VDS,
take place across the channel region and causes the negative charge (electrons) accumulation at the two sides of the channel near the source and the drain interfaces with channel and also in
Considering the Colinge et.al suggestion [47
] for saturation region, we have
This equation can be compared with the general expression of drain current for conventional MOSFETs in the saturation region or even in the accumulation mode [53
]. In addition, because of the presence of ohmic contacts for the majority carriers and their location, which is away from the channel edges, we will not have any ambipolar behavior. Unfortunately, the transistors showed leakage through the gate electrode when gate voltages exceeded −3
V. However, the device worked was acceptable for gate voltages smaller than −3
V and gave us some information to confirm our simple model.