In this section, we present our SAT-based ATPG method. Before the method is described in detail, we first provide definitions for fault modeling and Boolean Satisfiability.
A manifestation of a defect at the abstracted function level is called a fault.
In an IC, the difference between a defect and a fault can be explained as imperfections in the hardware and function, respectively. While in genomics, examples of biological defects can include mutations in the gene activation site, malformation of the protein folding, and problems in the gene product transport. Likewise, an example of a biological fault is a modification of the logical function representing a gene, producing the incorrect output. A stuck-at fault is modeled by assigning a fixed (0 or 1) value to a signal line (input or output of a logic gate) in the circuit.
An untestable fault is a fault which no test can detect. Untestable faults appear in two situations.
• Faults that are redundant, whose presence does not change the output behavior of the circuit.
• Faults that change the output behavior of the circuit, but no test (drug vector in the context of cancer therapy) can be generated to propagate or rectify the fault.
Stuck-at fault modeling
In the Boolean network model for a GRN, the activity of genes is modeled as a Boolean circuit. We assume the circuit is modeled as an interconnection of Boolean gates. A stuck-at fault is assumed to only affect interconnections (wires or nets) between gates. Each net can have one of two types of faults: stuck-at-1 or stuck-at-0 (s-a-1 and s-a-0, respectively). Thus, a net with a stuck-at-0 fault will always have a logic value 0, irrespective of the correct logic output of the gate (gene) driving the net.
As an example, consider the circuit of Figure comprising of an OR gate driving an AND gate. Also consider a stuck-at-1 fault at the output of the OR gate, which means that the faulty line remains 1 irrespective of the input state of the OR gate. If the normal (good) output of the OR gate is 1 (in the case where its inputs were < bc > = 01,10,11), then this fault will not affect any signal in the circuit. However, the input <bc > = 00 to the OR gate should produce a 0 output in the good circuit. The good (faulty) value 0 (1) is applied to the AND gate. If the input vector <abc > = 100, the good circuit output (true response) and faulty output would differ. Hence <abc > = 100 is called a test for the s-a-1 fault on the output of the OR gate.
A stuck-at-0 fault is modeled by inserting a two-input AND gate at the fault site as shown in Figure . The side input of the gate is driven by a signal which is set to 1 to simulate a fault-free site, or set to 0 to inject the s-a-0 fault. Similarly, the circuit with a s-a-1 fault is modeled by inserting an OR gate at the site. The side input of this OR gate is set to 0 to simulate a fault-free site, or set to 1 to inject the s-a-1 fault. These gates are inserted at every net (wire), allowing the simulator to inject faults at any site.
Note that drugs are modeled the same as stuck-at faults, wherein a drug that inhibits a gene is modeled as a s-a-0 "fault", while a drug that activates a gene is modeled as s-a-1 "fault". The gates for drug injection are inserted at the nets of the genes that they target.
Several ATPG algorithms [5
], including the method proposed in this paper are based on Boolean Satisfiability (SAT) and utilize the stuck-at fault model. We begin with an overview of SAT, followed by a SAT-based formulation of the ATPG problem.
or a literal
function is a binary variable x
or its negation
is a disjunction (logical OR) containing literals (example:
A Conjunctive Normal Form (CNF)
consists of a conjunction (AND) of m
. Each clause ci
consists of disjunction (OR) of ki
literals. A CNF S
if it evaluates to 1. Satisfying S
is equivalent to satisfying all ci S
Given a Boolean formula S (on a set of binary variables X) expressed in CNF, the objective of SAT is to identify an assignment of the binary variables in X that satisfies S, if such an assignment exists.
For example, consider the formula
. This formula consists of 3 variables, 2 clauses, and 4 literals. This particular formula is satisfiable, and a satisfying assignment is (a
) = (0,0,1) or
. There are several extensions to the SAT problem. One such extension of interest is All-SAT
. For a SAT formula, there may exist many satisfying assignments. The objective of All-SAT is to find all
satisfying assignments. Another useful extension is Weighted partial Max-SAT
(WPMS) which aims to satisfy a partial set of clauses. In WPMS, each clause in the CNF is identified as a hard clause or soft clause. Each soft clause is associated with a weight. The problem then is to identify an assignment that satisfies all
hard clauses while maximizing the total weight of the satisfied soft clauses.
SAT-based formulation for stuck-at fault model
In the SAT based ATPG method, we first generate a formula in CNF to represent tests for the fault. To do so, the circuit from the stuck-at fault model must be converted to a CNF. Every gate (gi) of the circuit has CNF formula (Gi) associated with it, which represent the function performed by the gate. The formula is true iff the variables representing the gate's inputs and outputs take on values consistent with its truth table.
For example, consider a 2-input AND gate (gj) with the lines x and y as inputs and z as output. The CNF formula (Gj) for the AND gate is written as:
A CNF formula for the entire circuit S is obtained by forming the conjunction of the CNF formulas for all the gates of the circuit. If there are n gates in the circuit, then the CNF formula S for the entire circuit is written as:
When all the s-a-0 and s-a-1 variables are set to false (0), the CNF formula S describes the good (fault-free) circuit behavior. The faulty circuit is a copy of the fault-free circuit, with faults (s-a-0 or s-a-1 variables) injected at the gates to be affected by faults.
We explain our approach using a simple example. Assume we are given the BN network from Figure , which has two gates g1 and g2, primary inputs a, b, c, and primary output z. Also assume and we want to model a stuck-at 1 fault on the output of gate g1 as shown in the figure. From our stuck at model, we insert an OR gate g3 at that location. We label the output of g3 as e, which is now an input to gate g2. The gate g3 has two inputs, d (the output of gate g1) and a side input f. With all inputs and outputs labeled, we obtain the CNF formula for each gates and the entire circuit.
The value of f
, the side input to gate g3
, determines whether the stuck-at 1 fault is activated or now. To activate the fault, f
is set true by adding a clause (f
) to the CNF, thus S
1 · G2
). Likewise, to deactivate the fault, f
is set false by adding the clause
to the CNF, thus
. With our CNF formula for the circuit, we now describe several usage cases employing this CNF in SAT.
Implementation of fault and drug simulation
Case 1: Single stuck-at fault identification
In this method, we find all single stuck-at faults which are non-redundant, as well as the faulty outputs that they generate. To proceed with this method, we first simulate the original circuit to determine the correct fault-free output. The circuit is simulated using our SAT formulation in the fault-free and drug-free model for a specified primary input value, and the resulting primary output value for the true response is saved as Z0.
The next step is to find all faults which are non-redundant. To avoid having to do an exhaustive search on all single stuck-at faults, we perform an All-SAT on the circuit S where we constrain the output to be not Z0. Assuming n output signals, this constraint is formed as the clause C1,
is the variable corresponding to the ith
Furthermore, we also add a constraint to S that the circuit contains only one fault that is injected at a time. This second constraint C2 is formed by writing clauses of all pairwire combinations of faults, where k is the number of stuck-at faults and fi is the ith fault.
We now form a new CNF S1 = S · C1 · C2. The resulting All-SAT on S1 is a list of all non-redundant single stuck-at faults and their faulty output. These faults are flagged for drug simulation using any of the next three cases.
The results from this case can also be used immediately in several ways. For example, this method classifies for each single stuck-at fault whether it is redundant or non-redundant. That is, any fault which is redundant does not produce an incorrect output, and can be ignored from a therapy standpoint. In a second example, the faulty output from the stuck-at model can be compared to a previously measured output from expression data, in order to identify which genes are potentially faulty. This information can be used to target genes for potential drug development, avoiding genes that are untestable.
Case 2: Fault rectification with fewest drugs
In the presence of a particular fault, the problem is determining whether a selection of drugs can rectify the circuit, i.e. change the faulty output to the correct output. If this is not possible, we want to obtain the "best" or "closest" output to the correct output, by using drugs. To do this, we guide the WPMS solver by assigning weights to the output states. For example, in the GF network used in our experiments, the fault-free output Z0 is assigned the highest weight (80) and remaining output states are assigned decreasing weights (70, 60, 50, etc.) based on increasing Hamming distance (1, 2, 3, etc.) from the fault-free output. We assume that faulty states that have a larger Hamming-distance have a more pronounced cancer proliferative effect.
Additionally, the selection of drugs to achieve the best output should use the least number of drugs to minimize the side-effects on the patient. To incorporate this in the WPMS solver, each drug that is not selected is given a weight of 1. The GF network example has 6 drugs, thus if no drugs are selected, then the cumulative drug weight is 6. Likewise, if all drugs are selected, the drug weight is 0.
Note that the output and drug weights are assigned in such a way as to avoid the situation where a less-desirable output (with few drugs) is chosen over a higher weight output with more drugs. We assume that from a clinical standpoint, the priority is to first produce the best possible output, and secondarily to use the fewest drugs required for that output.
All faulty circuits with non-redundant faults from Case 1 are augmented with the output and drug weights and simulated using WPMS. The WPMS solver will implicitly and deterministically find the assignment of drugs that achieves the best possible output and with the fewest drugs. The output values, selected drugs, and highest weight of the fault+drug circuits are recorded and compared with the drug-free circuits. An immediate result from this method is that a fault where the fault+drug circuit which obtains its best output with zero drugs is in fact an untestable fault, wherein no drug combination can improve the output.
In general, several stuck-at faults can be simultaneously present in the circuit. A circuit with n lines can have 3n - 1 possible stuck line combinations. This is because each line can be in one of the three states: s-a-1, s-a-0, or fault-free. All combinations (except one which has all lines in their fault-free state) are counted as faulty. In our implementation, multiple stuck-at faults can easily be modeled for rectification, by setting one or more lines to their faulty state.
Case 3: Fault rectification with minimal drug cost
In the previous case, all drugs are equal in terms of their weight. However, there may be a situation where we would want to differentiate the drugs based on some cost function based on characteristics such as price, number of side-effects, or ease of availability. For example, two drugs with few side-effects may be more desirable than one drug with many side-effects, if both drug selections produce the same output. As such, in the presence of a particular faulty circuit and desired output, the problem is determining a selection of drugs with lowest total cost.
Each drug that is not selected is given a weight proportional to its cost. In our example, we use the number of side-effects as the drug's cost. All faulty circuits with detectable faults from Case 2 are modified with the new drug weights. In addition, the output of the circuit is fixed to the best output as determined in Case 2. These circuits are then solved using WPMS to obtain the selected drugs with lowest cost.
Case 4: Determining therapy with fewest drugs and best coverage
From Case 2, we identify the drug selection that best rectifies a certain fault. However, in drug therapy, the fault location may be unknown. In this situation, a drug selection that rectifies all faults (or as many faults as possible) with the fewest drugs, is desirable.
For each faulty circuit (with a single fault), we find all combinations of 1, 2, and 3 drugs that yield the best output from Case 2. This is done by performing a WPMS All-SAT to find all satisfying drug selections with drug weight greater than or equal to d - 3, where d is the total number of drugs. Each drug selection (or vector) is analyzed to see how many testable faults are rectified or covered by it. The drug vector with the highest coverage and fewest drugs is recorded as a best candidate for therapy.