Drain current (IDS
) versus drain voltage (VDS
) curves under different gate voltages (VGS
) of the devices are shown in Figure . The threshold voltage (Vth
) is −1.5 and −0.25 V for III-V MESFET and MOSFET, respectively. In Figure a, a kink behavior was observed. The knee voltage which defines the transition between linear and saturation regions in the normal IDSVDS
curve was smeared as the channel is near pinch-off. This phenomenon is related to Fermi level pinning and electron trapping by surface states [20
]. A depletion region was created between gate and source/drain electrodes which results in reduced drain output current. When the gate bias is increased, the device behaves more like a typical FET. For the IDSVDS
curves of the MOSFET as shown in Figure b, the performance was improved. This is mainly due to the deposited Al2
dielectric layer on the surface of the GaAs channel. The Al2
high-k dielectric layer not only acts as a gate insulator, but also plays an important role of surface passivation [21
]. The significant performance difference between MOSFET and MESFET implies that devices with a three-dimensional FinFET structure inherently suffer from surface trap issue more seriously than conventional planar devices. This is primarily due to the additional exposed side walls of the fin-shaped channel (i.e., the channel has larger surface-to-volume ratio). Consequently, a good device passivation procedure preventing surface trap-induced effects is indispensable for III-V FETs with a FinFET structure to ensure high device performance.
I DS -V DScharacteristics with FinFET structure. (a) 0.5-μm III-V MESFET and (b) 0.5-μm III-V MOSFET.
The subthreshold characteristics of the devices were also evaluated to further verify the benefit of applying a FinFET structure to III-V MOSFETs. Figure shows the transfer curves of the devices measured at VDS
1 V. Device parameters such as drain-induced barrier lowering (DIBL), on current/off current (Ion
) ratio, and subthreshold swing (SS) were extracted. The calculated DIBL of MESFET is 120 mV/V (shown in the inset of Figure ), while the value is decreased to 47 mV/V for MOSFET. By introducing a dielectric film, the gate leakage current of the device can be reduced as shown in Figure . This is beneficial for improving the Ion
ratio of the device. The definition of Ion
can be found in the literature [22
]. The supply voltage VCC
is 1 V for parameter extraction. The MESFET has an Ion
ratio of 1.17
, and the ratio is improved significantly to 2.54
for MOSFET. The SS at VDS
1 V is 123 mV/decade for MESFET and 80 mV/decade for MOSFET. The low SS value of the MOSFET is an indication that the devices have low interface trap density and good gate controllability over the channel [8
]. These results further demonstrate that MOSFET outperforms MESFET in terms of subthreshold characteristics. As a result, the use of a MOS gate scheme is essential in the performance improvement of the III-V MESFETs. The extracted effective channel mobility in the linear region of the III-V nMOSFET was about 100 cm2
/V-s using the following expression:
], where μ
is the carrier mobility and Cgate
is the gate capacitance per unit area. The 3D III-V nMOSFET has a total gate width W
/gate length L
0.6:0.5 μm. The low value of the extracted channel mobility of the 3D III-V nMOSFET was possibly due to the high parasitic access resistance caused by the narrow fin in the source/drain (S/D) regions. Further improvement can be achieved by using a self-aligned S/D process or forming a heavily doped fin region in the S/D extension. In short, the comparison of electrical performance between 3D III-V nMOSFET and 3D III-V nMESFET is presented in Table . As shown in Table , when compared to conventional planar III-V MOSFETs, the fabricated MOSFET in this work with a FinFET structure exhibits very promising results under low-voltage operation. Although the TFin
of the GaAs fin is 200 nm, the SS value of the device with a 0.5-μm gate length is better than the published results of 1 μm
100 μm planar In0.2
As MOS-high electron mobility transistor [8
] which essentially has longer gate length and buried quantum well channel design with higher carrier mobility. The above results further confirm that the III-V MOSFET developed in this work exhibits excellent gate controllability over the channel due to the use of a 3D FinFET structure.
Subthreshold characteristics of the 0.5-μm III-V MOSFET with FinFET structure. Inset shows the characteristics of the III-V MESFET for comparison.
Electrical performance of 3D III-V nMOSFET and nMESFET with 0.6-μm gate width and 0.5-μm length
Ion/Ioff, on current/off current; VGS, gate voltage; VDS, drain voltage; Vth, threshold voltage; SS, subthreshold swing; DIBL, drain-induced barrier lowering; MOSFET, metal-oxide-semiconductor field-effect transistor; MESFET, metal–semiconductor field-effect transistor.