Nowadays, the scaling down (known as ‘More Moore’) of devices is coming to an end. To maintain a constant evolution of the device performances in the future, alternative ways must be explored. The main one is the device functional diversification and the three-dimensional (3D) integration (‘More than Moore’). The 3D integration is based on the use of the semiconductor volume to connect both sides of a silicon wafer [1
]. This technique enables the stacking of the dies and leads to an important surface gain. The through-silicon via (TSV) technology is the key parameter for 3D integration allowing through-silicon connections. This technique is based on the etching of TSV and then the filling of these through holes by a conductive metallic material such as copper or tungsten [1
The TSV are usually etched into the silicon using deep reactive ion etching (DRIE) [3
]. This technique requires both chemical and physical silicon attacks [5
] to achieve anisotropic etching of silicon. The Bosch process [6
] is often employed to reach high aspect ratio (HAR) structures. It consists of the alternative insertion into the etching chamber of two gaseous species: an etching one (e.g., SF6
) and a polymerizing one that immunizes the sidewalls from the SF6
attack. This enables the formation of versatile structures into the silicon wafer. Despite its high versatility, DRIE technique suffers of several limitations. The first limitation is the value of the via aspect ratio that can be attained. Indeed, this value is limited to around 30 or 40 because of homogeneity defects [7
]. Furthermore, the main issue of DRIE is the corrugation (or scalloping) development on the silicon sidewalls. This corrugation is directly imputed to the alternative steps of the Bosch etching process. The scalloping is known to be responsible for deposition conformity defaults.
The electrochemical etching of silicon leading to porous silicon formation is an alternative to DRIE for low-cost TSV fabrication. Indeed, macropore formation (pore diameter
nm and most of the time
μm) presents several advantages as compared with dry etching technique. In this case, the wafers are immersed into a HF-based solution (often mixed with solvents and/or surfactants) and an anodic current (or potential) is applied to the sample. The morphology of porous silicon is influenced by the substrate nature (its orientation, doping type, and concentration), the electrolyte composition (HF and additive concentrations), and the anodization parameters (applied current or potential, illumination, etc.) [8
]. To obtain HAR, high-density TSV, a low-doped (ρ
0.5 Ω cm) n-type (100)-oriented substrate can be employed. For example, HAR macropores (aspect ratios can reach 250 to 300) [9
] with ultra-high densities (>108
] can be achieved homogeneously on 6-in. wafers [11
]. These values are much higher than those reached by DRIE and very promising for the future TSV density increasing needs.
Most of the time, TSV are filled with copper because this metal owns one of the highest electrical conductivity. Copper thin films are often obtained by electrochemical deposition. This technique is a low-cost way to achieve large area, high conductivity copper layers. Copper electrochemical deposition into through holes is thus studied for almost two decades because conformal deposition into confined media is much more difficult than on flat surfaces [12
]. The chemistry of the electrolyte needs to be adapted to this constraint. Thus, several additives are commonly added to the H2
electrolytic mixture during the copper deposition to ensure void-free, high conductivity copper filling even into HAR structures [13
The first part of the present paper describes the different strategies to achieve conductive TSV from ordered macroporous silicon. Then, the conditions of HAR macropore array etching by silicon anodization were developed. After anodization, ‘almost’ through-silicon macropores were locally opened by backside photolithography. The through-silicon macropores were then filled with copper. Finally, these TSV were electrically characterized to determine the resistance of the conductive paths.
Different strategies of conductive through-silicon via localization
To achieve localized TSV, four strategies can be explored. Either the macropores or the seed layer can be localized on the sample in order to select the conductive regions. The simplest way would be the ordered macropore array localization (such as DRIE technique) because this technique leads to the formation of local, through-silicon macropore regions depending on the mask design (cf.
a). After anodization, a simple backside seed layer deposited on the whole surface of the wafer ensures the metal electrochemical bottom-up filling (Figure b,c) [14
]. However, this process is very difficult to perform because of macropore localization issues. Inert masking layers may be employed to protect some areas against the porous silicon formation, but over-etching is observed at the edge of unmasked regions [15
Figure 1 Selective TSV formation by macropore array localization. (a) Through-silicon macropores are locally etched by electrochemical etching through an inert mask. (b) The seed layer is deposited on the backside of the substrate. (c) The macropores are filled (more ...)
A second option could be the formation of macropore array on a whole sample and the localization of copper electrolyte penetration in the macropores by photolithography as described by Föll et al. [17
]. Figure illustrates the process flow. After the through-silicon macropore etching (Figure a), a masking layer is locally deposited on the pores to stop the penetration of the electrolyte (see Figure b). During the copper electrochemical deposition, the macropores in contact with the electrolyte are selectively filled with copper (Figure c). After the pore filling, the backside seed layer can be removed by a polishing technique (Figure d). The main issue of this process is the technique employed to locally mask a textured surface such as macropore arrays. It cannot be performed by usual photolithography.
Figure 2 Selective TSV formation by local macropore masking before copper electrochemical deposition. (a) Electrochemical etching of silicon leading to through-silicon structures. (b) Local masking of macropores limiting the electrolyte penetration into opened (more ...)
The third strategy is the seed layer local deposition onto through-silicon macropores. After silicon anodization leading to through-silicon macropore formation (cf.
Figure a), the seed layer is selectively deposited on the backside of the wafer (Figure b). For this purpose, ink-jet deposition technique as well as locally metalized contact wafer stacking can be employed. Since the copper can only grow on the conductive surface, the copper is limited to the seed layer areas (Figure c). Using this strategy, through-silicon via locally filled with copper may be obtained as already described in the literature [18
Figure 3 Selective TSV formation by local seed layer deposition. (a) Electrochemical etching of silicon leading to through-silicon macropore array formation. (b) Local deposition of the seed layer on one side of the sample. (c) The macropores sealed by the seed (more ...)
The last strategy is based on the local opening of almost through-silicon macropores [19
]. Deep macropores were etched, but the anodization was stopped before the backside opening (see Figure a). After silicon dioxide (SiO2
) thermal growth followed by backside photolithography, alkaline etching is performed to locally open the macropores (Figure b). The seed layer was deposited on the backside of the sample; thus, the filling of macropores is limited to ‘through’ regions (Figure c,d). This process was chosen to be tested because it can be performed using ordinary microelectronic tools. Finally, this process is much easier than direct macropore localization (strategy 1) because it limits the edge defects.
Figure 4 Selective TSV formation by local opening of almost through-silicon macropores. (a) Electrochemical etching of silicon leading to high aspect ratio structures. (b) Selective opening of the backside oxide mask followed by alkaline etching. This leads to (more ...)