In Figure , an example of topography and current images for two different biases, is presented for a (p) a-Si:H/(n) c-Si junction. At positive bias applied to the sample, conductive regions appear light in the current images, while for negative bias they appear dark. The current images clearly reveal a conductive interface layer between the c-Si substrate and the a-Si:H film. This layer is more conductive than both the c-Si and a-Si:H regions. This conductive interface layer was well observed on all samples for both (p) a-Si:H/(n) c-Si and (n) a-Si:H/(p) c-Si heterointerfaces whatever the a-Si:H layer thickness is. It is worth to note that the conductive layer is not an artifact that could come from the surface roughness. It can be clearly seen when current images are compared with the topography one. There exists one distinct boundary between the a-Si:H layer and c-Si wafer, and the detected conductive channel lies within c-Si substrate.
Figure 4 AFM pictures taken on a cleaved section of an ITO/(p) a-Si:H/(n) c-Si/ITO sample. Left: topography; middle: current image taken at an applied bias of +1.5 V. Right: current image taken at an applied bias of -1.5 V. Typical roughness was less than 5 nm. (more ...)
However, the quantitative results of the interface layer conductivity deduced from CP-AFM measurements have to be considered carefully. Indeed, the reliability of the latter is affected by the quality and nature of the contact between the conductive tip and the sample surface. The sample surface roughness, the AFM tip radius, shape and pressure are well-known factors driving local electrical measurements. Moreover, surface states can induce additional band bending at the tip-surface junction modifying significantly the conductance values [5
]. The CP-AFM scanning measurements can also be influenced by the oxidation process after cleaving the sample and the presence of a water meniscus between the tip and the surface that can also lead to tip-induced oxidation or trapping of carriers in localized states [6
]. The contact between the tip and the cleaved surface can behave as a metal-oxide interface that then determines the current flowing through the tip.
In order to minimize the effects of surface oxide and surface states, CP-AFM measurements were performed at LGEP under nitrogen atmosphere immediately after having dipped the sample in an HF solution. This treatment is known to passivate the silicon surface by reducing the density of silicon dangling bonds, thus minimizing the potential effect of surface states on the surface band bending. Figure illustrates an example of topographical and electrical image of the cleaved section obtained under these conditions with, from top to bottom, the n-type a-Si:H layer (= 300 nm) and the p-type c-Si substrate. Contrary to Figure , the ITO contact is not observed since it has been partially removed after the HF dip. Compared to results of Figure , with the improved measurement procedure, a conductive channel at the (n) a-Si:H/(p) c-Si interface is even more clearly observed. The topographic and electrical profiles along the heterointerface presented on Figure show a flat cleaved surface and a higher electrical contrast between the conductive channel and both the a-Si:H layer and the c-Si substrate. In addition, the electrical image in the c-Si also shows a region with increasing conductivity of about 1 μm width when sweeping away from the a-Si:H/c-Si interface. This can be linked to the depleted space charge region in the low-doped (p) c-Si (Na < 1015 cm-3), which has a width close to 1 μm.
Topography and electrical image obtained after HF dip at the cleaved section of an (n) a-Si:H/(p) c-Si heterojunction. Left: topography; right: resistance image.
Profile of local resistance across the (n) a-Si:H/(p) c-Si interface corresponding to Figure 5.
The existence of an interface conductive channel has also been evidenced by the planar conductance measurements. Indeed, it was shown that the planar conductance was orders of magnitude larger for the samples deposited on c
-Si substrates (both n
- and p
-type) than that measured on the a
-Si:H layer deposited in the same run on glass substrates. Activation energy of the conductance for the samples deposited on glass was found equal to about 0.35 and 0.2 eV for the (p
-Si:H and (n
-Si:H layers, respectively [8
]. These are typical values for doped a
-Si:H. The conductance for samples deposited on c
-Si had much lower activation energy, as can be seen in Figure . This high planar conductance measured on the samples deposited on c
-Si is in very good agreement with the presence of the conducting channel revealed by our CP-AFM measurements.
Figure 7 Arrhenius plots of the planar conductance measured on various samples. Red circles for (n) a-Si:H, blue squares for (p) a-Si:H, full symbols for layers deposited on c-Si wafer (on opposite doping type with respect to the deposited a-Si:H layer), open (more ...)
We attribute this thin conductive interface channel along with the low conductance activation energy to a strong inversion layer at the c-Si surface that is related to the band offset at the heterojunction.
In order to further demonstrate the existence of the strong interface inversion layer and the related contribution to the conductance, we used the AFORS-HET software [10
] to evaluate the free carrier profiles. We introduced the density of states (DOS) typical for n
-Si:H (band gap Eg
= 1.75 eV) consisting of two exponential band tails with characteristic energies kBTC
of 0.055 and 0.12 eV for the conduction and valence band, respectively, and with a pre-exponential factor of 2 × 1021
, and two Gaussian deep defect distributions of donor and acceptor nature being located at 0.58 and 0.78 eV above the top of the valence band, respectively, with a maximum value of 8.7 × 1019
and a standard deviation of 0.23 eV. A doping density of Nd
= 5.34 × 1019
was also introduced, setting the Fermi level EF
at 0.2 eV below the conduction band at 300 K, as suggested from the activation energy of the conductance data measured on (n
-Si:H samples deposited on glass. The doping density in the crystalline silicon was set at Na
= 7 × 1014
, as found from capacitance versus bias measurements [11
], and in agreement with the resistivity of our CZ c
Figure shows the calculated band diagram and the electron concentration profile for various values of the conduction band offset ΔEC = ECa-Si:H - ECc-Si, respectively. An inversion layer is indeed clearly seen in the interface region of c-Si when sticking increase of electron concentration with ΔEC is observed. On the contrary, increasing ΔEC leads to a stronger electron depletion in (n) a-Si:H close to the interface due to a stronger band bending.
Modeling of the (n) a-Si:H/(p) c-Si heterojunction at equilibrium for various values of the conduction band offset. (a) band diagram, and (b) free electron concentration profile.
Similar simulations were performed for the (p) a-Si:H/(n) c-Si heterojunction. The band gap of a-Si:H also was taken at Eg = 1.75 eV, and the position of the Fermi level was fixed at 0.45 eV, which is a reasonable value for p-type a-Si:H, in agreement with our conductivity measurements. After having introduced the a-Si:H parameters, we combined the a-Si:H layer with an n-type c-Si substrate with Nd = 2 × 1015 cm-3 (corresponding to the resistivity value) to simulate the (p) a-Si:H/(n) c-Si heterojunction. Calculated band diagram and evaluated hole concentration profiles for different values of valence band offset ΔEV = EVc-Si - EVa-Si:H are shown in Figure , respectively. Drastic increase of hole concentration is observed in (n) c-Si layer near the interface for increasing values of band offset, with the appearance of a strong inversion layer for ΔEV > 0.2 eV. Thus, simulations of both (n) a-Si:H/(p) c-Si and (p) a-Si:H/(n) c-Si heterojunctions show the appearance of a strong inversion interface region above a given value of band offset. The planar conductance can be related to the carrier density profile. Indeed, the conductance of the strong inversion channel can be written
Modeling of the (p) a-Si:H/(n) c-Si heterojunction at equilibrium for various values of the valence band offset. (a) band diagram, and (b) free hole concentration profile.
is the elementary charge, h
the length of the coplanar electrodes, L
the gap between them, μ
the mobility of the carriers in the strong inversion region, and N
the sheet carrier density, i.e., the integral over the c
-Si thickness of the carrier concentration. Carriers to be considered are the electrons for the (n
-Si interface and the holes for the (p
-Si interface. We calculated the values of N
as a function of the band offset and of the temperature. We thus were able to compute the planar conductance and compare it to the experimental data. This proved to be a very precise way to determine the band offsets in the (n
-Si system [12
], where a value of ΔEC
= 0.15 eV was found. In the (p
-Si system, the measured resistance profile was compared to the calculated resistivity profile across the heterojunction. Both profiles have very similar shapes, and the thickness of the strong inversion layer is of the same order of magnitude (50-100 nm). Further analysis of the CP-AFM measurements shows that a strong inversion layer only exists if the valence band offset is large enough, ΔEV
> 0.25 eV [13
]. A more detailed theoretical and modeling study including the effect of temperature dependence of the band gaps and of the DOS parameters in a
-Si:H is under way. It confirms our previous determination of conduction band offset and indicates that the value of valence band offset that best reproduces our experimental data is around ΔEV
= 0.4 eV.