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Logo of nihpaAbout Author manuscriptsSubmit a manuscriptHHS Public Access; Author Manuscript; Accepted for publication in peer reviewed journal;
Nano Lett. Author manuscript; available in PMC 2011 October 13.
Published in final edited form as:
PMCID: PMC2964282

Sub-100 nm channel length graphene transistors


Here we report high performance sub-100 nm channel length grapheme transistors fabricated using a self-aligned approach. The graphene transistors are fabricated using a highly-doped GaN nanowire as the local gate, with the source and drain electrodes defined through a self-aligned process and the channel length defined by the nanowire size. This fabrication approach allows the preservation of the high carrier mobility in graphene, and ensures nearly perfect alignment between source, drain, and gate electrodes. It therefore affords transistor performance not previously possible. Graphene transistors with 45–100 nm channel lengths have been fabricated with the scaled transconductance exceeding 2 mS/µm, comparable to the best performed high electron mobility transistors with similar channel lengths. Analysis of and the device characteristics gives a transit time of 120–220 fs and the projected intrinsic cutoff transit frequency (fT) reaching 700–1400 GHz. This study demonstrates the exciting potential of graphene based electronics in terahertz electronics.

Keywords: graphene transistors, self-aligned gate, nanowires, transit time, cutoff frequency

Graphene, the mother materials of all sp2 carbon allotropes, has recently become the most shining star in the carbon family due to its significant potential for fundamental studies and applications in future electronics.16 Graphene is characterized by a linear dispersion relation with the Dirac point separating the valence and conduction bands with a zero bandgap, which limits the achievable on-off current ratios but does not rule out analog radio frequency (RF) device applications.7 With the highest carrier mobilities exceeding 200,000 cm2/V·s, graphene is of particular interest for ultra-high speed electronics.8

Exploring graphene for future electronics requires effective integration of high quality gate dielectrics for top-gated devices. Deposition of dielectrics onto grapheme is of significant challenge due to the difficulties in nucleating high quality oxide on pristine graphene without introducing defects into the monolayer of carbon lattices.913 Importantly, we have recently developed a new strategy to integrate high quality high-k dielectrics with graphene by first synthesizing free-standing high-k oxide nanostructures at high temperature and then transferring them onto graphene at room temperature.1416 This strategy opens a new pathway to graphene-dielectric integration without introducing appreciable defects, and has enabled top-gated grapheme transistors with the highest carrier mobility (> 20,000 cm2/V·s) reported to date.14

Another limitation of top-gated graphene transistors reported to date is the substantial access resistance due to the significant gaps between the source-gate and gate-drain electrodes, where a large portion of the graphene channel in the gap area is not gated. It thus limits the achievable transconductance, and can have particularly adverse impact on short channel devices. With the size of the device shrinking into the deep nanometer regime, there is an increasing need for a more precise and reliable device fabrication process.

Here we report the fabrication of high performance sub-100 nm channel length graphene transistors using a self-aligned nanowire gate, which are transferred onto graphene through a physical assembly process at room temperature. The source and drain electrodes are defined through a self-alignment process to ensure nearly perfect alignment with the nanowire gate. The physical assembly of GaN nanowire gate preserves the high carrier mobility in graphene and the self-aligned source-drain electrodes minimize the access resistance and therefore afford transistor performance not previously achievable. We show that graphene transistors with sub-100 nm channel length can be readily fabricated with the extremely high scaled transconductance (2.3 mS µm−1) and on-current (~ 5 mA µm−1).

Figure 1 illustrates our approach to fabricate graphene transistors. In this process, single layer of graphene flakes were first mechanically peeled onto a highly doped p-type silicon substrate with a 300-nm thick thermal silicon oxide, and characterized using micro-Raman spectroscopy (Supplementary Fig S1). Highly doped n-type GaN nanowires were aligned on top of the graphene through a physical dry transfer process (Fig. 1a and Supplementary),15 followed by e-beam lithography and metallization (Ti/Au, 50/50 nm) process to define the external source, drain and gate electrodes (Fig. 1b). A thin layer of platinum (Pt) metal (10 nm) was then deposited on top of the graphene across the GaN nanowire, in which the GaN nanowire separates the Pt thin film into two isolated regions that form the self-aligned source and drain electrodes next to the nanowire gate (Fig. 1c–e).

Fig. 1
Schematic illustration of the fabrication process of the top-gated graphene transistor with a GaN nanowire as the self-aligned top-gate. (a), A GaN nanowire is aligned on top of graphene. (b), The external source, drain and top-gate electrodes are fabricated ...

In this device, the contact between the graphene and GaN nanowire creates a Schottky-like barrier (Fig. 1f) to prevent charge leakage between the graphene channel and the GaN nanowire gate, with the interface depletion layer in GaN nanowire functioning as a “semi-high-k” gate dielectric (k ~10), and GaN nanowire itself functioning as the local gate. Importantly, the depletion layer dielectric thickness may be controlled by tuning the GaN nanowire doping concentration. Additionally, the GaN nanowire can also form Schottky barrier with the self-aligned Pt source and drain electrodes, preventing the leakage between the nanowire gate and source drain electrodes.

Highly n-doped GaN nanowires were synthesized through a metalorganic chemical vapour deposition (MOCVD) process.1719 Scanning electron microscope (SEM) studies show that GaN nanowires used here typically have a nearly triangular cross section with rounded corner (Fig. 1e). The triangle cross section of the GaN nanowire with a flat side surface allows seamless contact between the nanowire gate and graphene to ensure excellent gate coupling that are critical for high transconductance. SEM and Transmission electron microscope (TEM) studies show that the GaN nanowires typically have a side width of 50–100 nm, and lengths on the order of 10 microns (Supplementary Fig. S2). The electron concentration of GaN nanowires is estimated to be n ~ 2×1019 cm−3 through electrical transport measurements (Supplementary Fig. S2).

Before the deposition of self-aligned Pt source and drain electrodes (Fig. 2a), we measured the graphene/GaN diode characteristics. Electrical measurements on graphene and GaN nanowire itself show linear current-voltage (I–V) characteristics (Fig. 2b). Importantly, the current transport across graphene/GaN junction shows clear rectification characteristics with a turn-on voltage around 3.0 V (Fig. 2c), suggesting a significant transport barrier exists between the graphene and the GaN nanowire. The existence of transport barrier between graphene/GaN junction allows using the GaN nanowire as a local top-gate for graphene transistors without significant gate leakage.

Fig. 2
The electrical properties of a GaN nanowire/graphene diode and transistor. (a), An SEM image of a GaN nanowire/graphene device. (b), I–V characteristics of the GaN nanowire and graphene, respectively. (c), Typical Schottky-diode-like I–V ...

We have measured the transfer characteristics, drain-source current Ids versus top-gate voltage VTG, of this locally gated transistor without self-aligned source-drain electrodes. The IdsVTG plot clearly shows that the graphene transistor can be modulated by the local nanowire gate, overturning from hole branch to electron branch within −1.5 to 2.5 V range (Fig. 2d), demonstrating the GaN nanowire can indeed function as an effective local gate electrode for graphene transistors. However, the gate modulation is less than 10%, which is smaller than the typical values observed in graphene transistors at room temperature (>50%).9, 2022 Obviously, the access resistance dominates the transport in this device because the GaN nanowire local gate only modulates a very small portion of the entire graphene channel.

To reduce the access resistance and improve the graphene transistor performance, self-aligned source and drain electrodes were deposited using a 10-nm thick Pt metal thin film to ensure precise positioning of the source and drain edges with the gate edge (Fig. 1d and e). Figure 3a shows a typical device with 100 nm nanowire gate and 2 µm channel width. With the self-aligned Pt source-drain electrodes, the gate-source leakage remains small compared to the channel current (Supplementary Fig. S3), and therefore would not significant affect the transistor characteristics. Importantly, the Ids-VTG transfer curve recorded for the self-aligned device shows a current modulation of more than 50% (Fig. 3b), comparable to the typical values observed in graphene transistors, suggesting the access resistance is largely removed through the self-alignment process. The hysteresis of Ids-VTG sweep is about 0.2 V in ambient conditions (Supplementary Fig. S4). The Ids-Vds output characteristics at various gate voltages (VTG = −0.5, 0.0, 0.5, 1.0, and 1.5V) show that this device can deliver a significant on-current of 10 mA at Vds = 1 V and VTG = −0.5 V (Fig. 3c). The transconductance gm=dIdsdVg can be extracted from the Ids-VTG curve (Fig. 3d). A peak transconductance of 4.6 mS is obtained at Vds = 1 V in our device, resulting a scaled transconductance of 2.3 mS/µm considering the 2 µm channel width of this device. Significantly, this scaled transconductance is nearly one order of magnitude better than the graphene transistors reported to date (Table 1).7, 2326 Additionally, the short channel graphene transistors afford exceptionally high current density (Supplementary Fig. S5). Considering the device dimension (assuming 0.35 nm thickness), a normalized current density of as high as 2.3×109 A/cm2 is achieved at Vds=1.8 V before the device breaks down, which exceeds the best value previously reported in graphene devices,27 and is comparable to that of metallic SWNT, or more than 3 orders of magnitude greater than those in typical metals such as copper.28, 29

Fig. 3
Room temperature electrical properties of the self-aligned graphene transistor. (a), An SEM image of a self-aligned graphene device with a GaN nanowire gate. The scale bar is 2 µm. (b), Transfer characteristics at Vds = 1 V for the device using ...
Table 1
The critical device performance parameters of top-gated graphene transistors at Vds = 1V. The relevant data were extracted from a few representative literatures with the transconductance gm scaled to Vds= 1V assuming a linear Ids-Vds relation. The transit ...

To determine the gate capacitance, we have measured the device conductance as a function of both VTG bias and back-gate (VBG) (Fig. 3e). From these measurements, we can obtain Dirac point shifts in the top-gated configuration as a function of the applied VBG (Fig. 3f), which gives the ratio between top-gate and back-gate capacitances, CTG/CBG ≈ 42. Using the back-gate capacitance value of CBG = 11.5 nF/cm2, the top-gate capacitance is estimated to be CTG = 483 nF/cm.20, 21

To precisely determine the graphene channel length, we have used SEM to measure the gap width (channel length) between the Pt source and drain electrodes (Supplementary Fig. S6). The graphene channel can be exposed and observed with SEM when the nanowire gate is removed by a brief sonication process. The channel lengths of the resulting graphene transistors are mainly determined by nanowire side width so that variable graphene channel lengths in the sub-100 nm regime can be readily obtained using different sized nanowires. We believe this approach is fundamentally scalable and may be extended for the fabrication of sub-10 nm channel length graphene transistors by employing smaller nanowires.

An important benchmark of transistor performance is the cut-off transit frequency (fT). In general, the intrinsic cut-off frequency of a transistor is determined by charge carrier transit time (τt) across the channel length (Lgate). The cutoff frequency is described as below:30,31



where C is the gate capacitance, and gm is max transconductance. For the device shown in Figure 3, the projected transit time τt and intrinsic fT at Vds = 1V is about 0.19 ps and 840 GHz, respectively, which is about 4 times faster than that of silicon MOSFET (e.g. about 200 GHz for a ~ 90 nm Si-MOSFET)30 and comparable favourably to that of InP-based high electron mobility transistors of similar channel length,30,32 and faster than all previous reports of graphene devices (Table 1)7, 2326.

Figure 4a and 4b show a summary of the projected transit time τt and intrinsic fT for the self-aligned graphene transistors of variable channel lengths. These plots show that an intrinsic cut-off frequency fT exceeding 1 terahertz can be reached in sub-70 nm channel length devices. Nonetheless, it should be noted that at such high speed, the transistor performance may start to be limited by gate delay, particularly considering the relatively large resistance of the GaN nanowire gate used here. Our analyses shown in these only give an upper limit of the intrinsic fT that can be achieved in our device design without considering the limitation of the gate delay. Future studies using lower resistance (metal) nanowire gate electrode could reduce the gate delay, and enable graphene transistor operation in terahertz regime.

Fig. 4
Channel length scaling of the sub-100 nm graphene transistors. (a), Transit time τt at Vds = 1 V, versus channel length for several self-aligned graphene devices of variable channel lengths, (b), The projected intrinsic cut-off frequency fT at ...

It is important to understand how the intrinsic cutoff frequency scales with gate length (Lgate). In a typical short-channel transistor with high fields, the steady-state carrier velocity saturates. At this point, the carrier mobility becomes less relevant to device performance and the carrier saturation velocity becomes an important measure of carrier transport. The transit time and cutoff frequency can also be described by:34



where vdrift is carrier drift velocity. The drift velocity (vdrift) of our devices can be derived by: vdrift = τt·Lgate (Fig 4c). A nearly constant vdrift of ~ 4.3×107 cm/s is obtained, comparable to the carrier saturation velocity reported in previous experimental and theoretical stduies.21,30,35 Using vdrift of ~ 4.3×107 cm/s, we can predict the ‘intrinsic’ cutoff frequency of graphene transistors: fT,intrinsic ≈ 70 GHz/Lgate(in µm), which is comparable to that of the very best high electron mobility transistors based on III–V semiconductor materials.30

In summary, we have described the fabrication sub-100 nm graphene transistors using a self-aligned approach. The unique device layout ensures that the edges of the source, drain, and gate electrodes are automatically and precisely positioned such that no overlapping or significant gaps exist between these electrodes and thus minimizes the access resistance. The fabrication approach allows integration of top-gate electrode without introducing damage into pristine graphene lattice and thus retains the high electronic performance of graphene, to enable graphene transistors with several significant advantages, including unprecedented drive current, transconductance and intrinsic cutoff frequency in graphene transistors. These studies thus open a new avenue to high performance graphene transistors that can lead to exciting opportunities in graphene-based high-speed high-frequency electronics.

Supplementary Material



We acknowledge Electron Imaging Center for Nanomachines (EICN) at UCLA for the technical support of TEM, Nanoelectronics Research Facility at UCLA for technical support of device fabrication. X.D. acknowledges support by NSF CAREER award 0956171 and the NIH Director’s New Innovator Award Program, part of the NIH Roadmap for Medical Research, through grant number 1DP2OD004342-01.


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