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Graphene has attracted a great deal of interest in the past several years.[1–5] New physics has been predicted and observed, such as ultrahigh carrier mobility, electron-hole symmetry and quantum hall effect,[2, 4, 7–9] and the strong suppression of weak localization.[10–12] For mainstream logic application, graphene nanoribbons (GNRs), as thin strips of graphene or unrolled carbon nanotubes, are predicted to be semiconducting due to edge effects and quantum confinement.[13–15] Recent experimental studies have also demonstrated that GNRs can effectively function as a semiconducting channel for room-temperature field-effect transistors.[16–22] By varying the width of GNRs at selected points, it is also possible to create graphene quantum dots within a GNR for single electron transistors. These studies represent important advances in GNR based electronics. However, most of the efforts to date employ a silicon substrate as a global back gate and silicon oxide as the gate dielectrics. While such a device has led to many interesting scientific discoveries, it will be of limited use for practical applications due to the high gate switching voltage required and the inability to independently address multiple units on the same chip.[17, 20, 21] Top-gated devices with high-k dielectrics can significantly reduce the required switching voltage and allow independently addressable device arrays and functional circuits, and therefore are of significant interest.
The insulating gate dielectric is an essential component of a transistor, which can significantly impact the critical device parameters including transconductance, subthreshold swing and frequency response. High-k dielectrics have been actively pursued to replace SiO2 gate insulator for silicon devices in the deep nanometer regime. High-k gate insulators can afford high capacitance without relying on ultrathin film thickness, thus can greatly reduce the required gate switching voltage and suppress direct-tunnelling leakage current from the gate. Signifincant efforts have been directde to the integration of high-k dielectric materials, e.g., zirconium oxide (ZrO2) or hafnium oxide (HfO2), with active semiconductor materials (e.g., silicon, semiconductor nanowires or carbon nanotubes) and have enabled devices of extraordinary performance.
Exploring graphene for future electronics requires effective integration of high quality gate dielectrics, in particular the high-k dielectrics. However, it has been rather challenging to deposit oxide dielectrics onto graphene without introducing defects into a monolayer of carbon lattice.[26–28] The deposition of high-k dielectrics is usually achieved using atomic layer deposition (ALD), which requires reactive surface groups. Functionalization of graphene surface for ALD either introduces undesired impurities or breaks the chemical bonds in the graphene lattice, inevitably leading to a significant degradation in carrier mobilities.[29, 30] Therefore, to develop an approach that can deposit high-quality high-k dielectrics without damaging the surface bonds of pristine graphene lattice remains a critical challenge towards high-performance, graphene-based electronics.
Here we describe an entirely new method for integrating GNRs with high-k dielectrics by first synthesizing high-k ZrO2 nanowires at high temperature, and then transferring them onto graphene through a dry transfer process at room temperature. This physical assembly approach can allow flexible integration of distinct materials that are normally not compatible due to material or process incompatibility, and has been used to combine variable nanostructures to enable unique new functions that are not normally possible.[31–33] Exploiting this approach for graphene dielectric integration preserves the integrity of the graphene lattice and affords top-gated GNR devices with unprecedented transconductance of 2.0 mS μm−1, and carrier mobility of ~1300 cm2V−1s−1. Furthermore, multiple independent addressable top-gated GNR transistor arrays can be readily achieved to allow functional circuits.
Figure 1 illustrates our approach to fabricate top-gated GNR transistors using dielectric nanowires as the high-k gate insulator. Mechanically peeled graphene flakes on silicon substrate were used as the starting materials in our initial studies. Dielectric nanowires were aligned on top of the graphene through a physical dry transfer process, followed by an e-beam lithography and metallization process to define the source and drain electrodes (Fig. 1a). Oxygen plasma etching was then used to remove the exposed graphene, leaving only the graphene protected by the dielectric nanowire and the source drain electrodes (Fig. 1b). An additional attribute of using nanowire dielectric is that narrow graphene channels (e.g., GNR) can be automatically defined by the nanowire mask during the oxygen plasma etching process. The top gate electrode was lastly fabricated on top of the dielectric nanowire (Fig. 1c). A typical GNR device consists of source, drain, and top gate electrodes (Ti/Au, 50 nm/50 nm), ZrO2 nanowire as the top-gate dielectric, a highly doped p-type silicon substrate (<0.004 ohm·cm) as the back gate, and a 300-nm thermal silicon oxide layer as the back-gate dielectric.
Zirconium oxide (ZrO2) is an excellent high-k dielectric material with multiple desirable characteristics, including a high dielectric constant (~23), a wide band gap (5.1 – 7.8 eV) and good thermal stability.[34, 35] ZrO2 nanowires were grown at 1000 °C through a chemical vapour deposition process in a tube furnace with ZrCl4 powders as the precursor. Scanning electron microscopy (SEM) image shows that ZrO2 nanowires are about several tens of microns in length and 40–100 nm in diameter (Fig. 2a). TEM and SAED studies reveal that ZrO2 nanowires are amorphous (Fig. 2b and inset). Energy dispersive x-ray (EDX) analysis of the nanowires shows only zirconium and oxygen signals, suggesting high purity for the ZrO2 nanowires (Fig. 2c).
In our fabrication, the ZrO2 nanowire functions as a nanoscale etch mask to define a narrow GNR with width in the 10–20 nm regime through aggressive over etching (inset, Fig. 2d) as well as top-gated dielectrics for the GNR transistor (Fig. 2d). Electrical transport studies of the top-gated device were carried out under an ambient condition at room temperature. Before starting transistor characterization, we first tested the gate leakage across the ZrO2 dielectric nanowire. Importantly, the tunnelling leakage current between the gate and GNR channel was negligible in the gate voltages range of ±2V (Fig. 2e). This measurement demonstrates that the ZrO2 dielectric nanowire can function as an effective gate insulator for top-gated GNR transistors.
The drain-source current (Ids) versus drain-source voltage (Vds) plot at various top-gate voltages (VTG) shows the GNR transistor output characteristics (Fig. 2f). The device conductance decreased as the gate potential increased towards positive direction and increased as the gate potential increased towards negative direction, suggesting that the GNR was p-doped, which can be attributed to edge oxidation or the physisorbed O2 from ambient or during the device fabrication process. The output characteristics shows that device can deliver an on-current of 28 μA at Vds = 1 V and Vg = −1.0 V (Fig. 2f).
Figure 2g shows the transfer characteristics drain-source current Ids versus top-gated voltage VTG curves for the same device at different drain source voltages. The device shows a room temperature on/off ratio of ~12 at Vds = 0.1 V, consistent with a GNR with an estimated width of ~15 nm.[18, 20] To evaluate the top-gated devices versus standard back-gated devices, we also measured the transfer characteristics in both the top-gated configuration (Ids-VTG) and back-gated configuration (Ids-VBG) (Fig. 2h). Significantly, the gate voltage swing required to achieve a similar current modulation in top-gate configuration is more than one order of magnitude smaller than that in back-gate configuration. Transfer characteristics show a top-gated GNR transistor using ZrO2 nanowire dielectric can be switched on and off with only ~1 volt of gate swing (red curve in Fig. 2h), in contrast to 10–40 V required for the back-gated configuration (black curve in Fig. 2h).[18, 20] The transconductance of the device can be extracted from the Ids-VTG curve. The gm at Vds = 1V is about 29 μS in the top-gated configuration (Fig. 2i), more than 12 times larger than that of the back-gated configuration (~2.3 μS, see the inset in Fig. 2i).
To further understand the device performance, it is important to determine the gate capacitance, which is not straightforward due to the complex geometry. To this end, we have employed three-dimensional finite element method to calculate the capacitance of the device, which yields an electrostatic capacitance (Ce) of 1170 nF/cm2 for a 15-nm ribbon under a 50-nm ZrO2 nanowire. Taking the top-gate capacitance (Ctop) as being the serial combination of the electrostatic capacitance (Ce) and the quantum capacitance (Cq), we can obtain Ctop = CqCe/(Ce+Cq) = 738 nF/cm2 assuming Cq = ~ 2000 nF/cm2. Based on standard transistor model, we calculated the hole mobility , the highest value obtained in GNR devices.
It is important to compare the top-gated GNR devices with the state-of-the-art silicon MOSFETs. The effective on current Ion for an FET device is usually characterized at Vds= Vg(on-off) = Vdd, where Vg(on-off) is the gate voltage swing from off-to on-state and Vdd is the power supply voltage. Considering Vds = Vg(on-off) = Vdd = 1V, the Ion of our device at Vds =1V and 1 V gate swing from the off state is ~25 μA. Taking the channel width of the GNRs as ~15 nm, we obtain the scaled values of Ion and gm of our device to be ~1.7 mA mm−1 and ~2.0 mS mm−1, already exceeding the values of 0.7 mA mm−1 and 0.8 mS mm−1 in sub-100-nm silicon p-MOSFETs and comparable to those of n-MOSFET devices employing high-k dielectrics. This is significant because high transconductance is critical to transistor performance and voltage gains of transistor-based devices including amplifiers and logic gates.
These studies demonstrate that ZrO2 nanowires can also function as effective gate dielectrics for high performance top-gated GNR devices. It should be noted that the current device has a relatively large channel length (~500 nm) and large dielectric thickness (ZrO2 nanowire diameter ~50 nm). It is reasonable to expect that the on current and transconductance can be further improved by shrinking the channel length and decreasing dielectric nanowire diameter. With smaller nanowires, we also expect that top-gated devices with higher on/off ratios can be achieved. Furthermore, with the top-gated devices, multiple GNR FETs and FET arrays can be readily fabricated with independently addressable top gates (Fig. 3a and b), and therefore allowing for diverse electronic functions. For example, a logic OR gate is obtained with two independent gate electrodes fabricated on a GNR in conjunction with a loading resistor (Fig. 3c). The OR function occurs because the output voltage is low only when input to both gates are at low voltages (Fig. 3d). When one or both gates are at high voltages, the GNR channel is electrically shut off, resulting in a high output voltage.
In summary, we have developed a new strategy to integrate high-k dielectrics for top-gated GNR transistors. Using the high-k oxide nanowires as the gate dielectrics and etch mask, high-performance, top-gated GNR transistors have been fabricated with the highest transconductance (29 μS per GNR, 2 mS/μm) and mobility (~1300 cm2/Vs) reported for GNR transistors to date. With the top-gated devices, independently addressable GNR device array and a logic OR gate have also been demonstrated for the first time for GNR devices. This method opens a new avenue to integrate high-k dielectrics on GNRs. With further optimization of dielectric nanowire growth and assembly process to precisely control their physical dimension and spatial location, large arrays of top-gated GNR transistors or circuits can be envisioned.
ZrO2 nanowires were grown at 1000 °C by a chemical vapor deposition process in a tube furnace with ZrCl4 powders as the precursor. In brief, the ZrCl4 powder in a quartz boat was placed at the upstream with a temperature of ~200 °C and a piece of silicon was placed at the center of the tube furnace as the deposition substrate at a temperature of 1000 °C. Form gas (5% H2 in Ar) with a flow rate of 200 sccm was used as the carrier gas and the reaction medium. The temperature was maintained for 2 hours and then naturally cooled to room temperature. The microstructures and morphologies of the ZrO2 nanowires were characterized by a JEOL 6700 scanning electron microscope (SEM). The lattice image of the ZrO2 nanowires was observed by an FEI Titan high-resolution transmission electron microscope (HRTEM) with energy-dispersive X-ray spectroscopy (EDX). The height and width were obtained using atomic force microscope (AFM, Veeco Dimension 5000).
The overall process involves physical transfer of ZrO2 nanowires directly from a nanowires growth substrate to a graphene substrate via contact printing. Specifically, a graphene device substrate was first firmly attached to a benchtop, and the nanowire growth substrate was placed upside down on top of the graphene substrate such that the nanowires were in contact with the graphene. A gentle manual pressure was then applied from the top, followed by slightly sliding the growth substrate. The ZrO2 nanowires were aligned by sheer forces during the sliding process. This process resulted in the direct dry transfer of ZrO2 nanowires from the growth substrate to the graphene substrate. The sample was then rinsed with isopropanol, followed by nitrogen blow-dry, in which the capillary drying process near the nanostructure could help the nanowires be firmly attached to the substrate surface.
Oxygen plasma (Diener Electronic) was used to selectively etch away the unprotected graphene region and leave graphene ribbons underneath the ZrO2 nanowires mask protection. The etching time was about 160 s at a power level of 40 W. The electrical transport properties were measured by a Lakeshore probe station with home built data acquisition system in ambient condition at room temperature.
We acknowledge Electron Imaging Center for Nanomachines (EICN) at UCLA for the technical support of TEM, Nanoelectronics Research Facility at UCLA for technical support of device fabrication. Y.H. acknowledges support from the Henry Samueli School of Engineering and an Applied Science Fellowship. X.D. acknowledges support by the NIH Director’s New Innovator Award Program, part of the NIH Roadmap for Medical Research, through grant number 1DP2OD004342-01.
Dr. Lei Liao, Department of Chemistry and Biochemistry, University of California, Los Angeles, CA 90095 (USA)
Jingwei Bai, Department of Materials Science and Engineering and, University of California, Los Angeles, CA 90095 (USA)
Yungchen Lin, Department of Materials Science and Engineering and, University of California, Los Angeles, CA 90095 (USA)
Dr. Yongquan Qu, Department of Chemistry and Biochemistry, University of California, Los Angeles, CA 90095 (USA)
Prof. Yu Huang, Department of Materials Science and Engineering and, University of California, Los Angeles, CA 90095 (USA). California NanoSystems Institute, University of California, Los Angeles, CA 90095 (USA)
Prof. Xiangfeng Duan, Department of Chemistry and Biochemistry, University of California, Los Angeles, CA 90095 (USA). California NanoSystems Institute, University of California, Los Angeles, CA 90095 (USA)