shows a die photograph of the 5.4 × 4.7 mm2
INI3 chip, which was fabricated in a commercially available 0.6-μ
m 2P3M BiCMOS process (X-FAB Semiconductor). The bulk of the layout area is consumed by a 10 × 10 array of neural signal amplifiers with bond pads that match the 400-μ
m pitch of a UEA, allowing nontoxic AuSn flip-chip assembly to the back of the array. A 5-mm gold coil can be attached to the back of the chip and used for receiving power and command signals [9
]. shows a prototype of the assembled Integrated Neural Interface consisting of a UEA, a microchip, and a power/command receiving coil. Up to three 0402-size (1.0 ×0.5 × 0.5 mm3
) passive surface-mount components (e.g., capacitors) can also be bonded to the back of the UEA and connected to the chip via backside metallization. We report here the operation of the INI3 microchip alone, without integration with the UEA, and include the photograph of the fully-integrated version in to convey our conception of how it can be fully implanted.
Microphotograph of 5.4 × 4.7 mm2 INI3 wireless neural recording chip, fabricated in a commercially available 0.6-μm 2P3M BiCMOS process.
Fig. 2 Photograph of prototype INI assembly (side view and top view). The integrated circuit is bonded to the back of a UEA, and a gold 5-mm power/command receive coil is placed over the back of the chip. A surface-mount 100 nF capacitor is visible in the lower (more ...)
Each on-chip amplifier has a gain of 60 dB with globally-programmable high- and low-frequency cutoffs that typically pass signals between 250 Hz and 5 kHz. One of the 100 amplifier channels has a low-frequency cutoff below 0.1 Hz to allow for the recording of local field potentials (LFPs). One user-selected amplifier is digitized at 15.7 kSps by a 10-bit successive-approximation analog-to-digital converter (ADC). A resolution of 10 bits allows for an electrode-referred quantization step of 2.0μV—less than half the rms noise level of the amplifier—with a full-scale range of ±1.0 mV, which is larger than most spikes. Digitizing all 100 channels in parallel would produce prohibitively high data rates given the power constraints of our RF transmitter.
Instead, we limit the telemetry data rate to practical levels by connecting 100 “spike detector” circuits to the amplifier array (see ). These spike detectors use comparators to detect neural action potentials (spikes) that exceed a user-programmable threshold either in the positive or negative direction. The 6-bit DACs used to set individual thresholds for each channel are incorporated into the 100 neural amplifier blocks. The programmable threshold levels also accommodate small offsets (on the order of 20μ
V, input referred) that vary across the amplifier array. The 100 latched comparators used for threshold crossing detection are grouped above the amplifier array to separate noisy digital circuits from sensitive analog amplifiers. The design strategies used to minimize amplifier power dissipation and reduce data rate have previously been described in [10
]. The use of simple, single-threshold-based spike detectors greatly reduces the required telemetry data rate but does not permit spike sorting if multiple neurons are observed on the same electrode. By simultaneously transmitting the fully-digitized waveform from one user-selectable amplifier, the spike detection thresholds may be easily set to the desired levels.
Functional block diagram of INI3 microchip.
As shown in , additional on-chip circuits rectify the ac voltage on the power receiving coil and produce a regulated 3.3 V dc supply for the chip. (The chip can function properly with a supply voltage from 3 to 4 V.) A 2.765-MHz inductive link supplies power to the chip; additional circuits recover this frequency and divide it by eight to produce a 345.6 kHz on-chip system clock with 50% duty cycle. Commands are sent to the chip by modulating the amplitude of the power signal. An on-chip command receiver detects amplitude changes in the unregulated voltage, waits for a specific 8-bit header signal, then reads in 852 control bits at a rate of 16 kbps. The control bits are used to set spike detection threshold levels and polarities, select a channel for the ADC, power down amplifiers that are not being used, set amplifier bandwidths, and configure the RF transmitter (see [3
] for more circuit details).
To relay ADC and spike detector telemetry data to an external station, we implement a frequency-shift keying (FSK) RF transmitter operating in the FCC-approved 902–928 MHz ISM (Industrial, Scientific, Medical) band. Prior versions of the INI chip employed a power-optimized CMOS LC
voltage-controlled oscillator (VCO) as a wireless transmitter [3
]. This configuration required a high-resolution DAC to set the carrier frequency through the analog VCO control voltage. This approach was highly susceptible to frequency drift due to supply noise and temperature and power supply variations because the VCO was operated on a high-gain portion of its tuning curve.
To combat the problem of temperature and supply dependence, the transmitter core has been redesigned as a digitally-controlled oscillator (DCO), shown in . The architecture of a DCO is identical to a VCO, but rather than relying on the output voltage of a DAC to control the varactor capacitance, the capacitance in a DCO is directly controlled by an 8-bit digital control word (see also [11
]). The measured tuning characteristic, shown in , is nearly linear and exhibits a temperature dependence of −96 ppm/°C from 35 C° –39 °C (four times better than previous INI VCOs).
DCO schematic without FSK varactors (only four bits shown for simplicity) and accumulation-mode MOS varactor C-V characteristic (inset).
DCO tuning characteristic with measured output spectra for adjacent tuning codes 78, 79, and 80 (green, blue, red) from a range of 0–255.
Direct digital control of the capacitance is accomplished by taking advantage of the sigmoidal C-V curve of an accumulation-mode MOS varactor (see inset). The small, unit-sized varactors are divided into eight binary-weighted groups (only four bits are shown in for simplicity), and the control terminal of each group is connected to one of the bits of the control word. When the ith control bit is switched from 0 to 3 V, the total tank capacitance is decreased by 2i Δ C, corresponding to an increase in frequency. Though the relationship between frequency and capacitance is nonlinear, over the frequency range of interest the nonlinearity is mild and acceptable as illustrated in . This technique has no impact on the power dissipation of the oscillator. Furthermore, it is more compact than an approach employing switches and fixed capacitors, and it does not degrade the tank Q. This DCO design reduces temperature and supply dependence as compared to a traditional VCO because all of the varactors are operated at the extremes of the C-V characteristic where the capacitance is far less sensitive to small changes in the control voltage (see inset).
This digital tuning technique is also used to implement FSK modulation (see inset). The varactors used for modulation (not shown in ) are approximately half the size of the unit varactor in the tuning array. With two additional control bits, the FSK frequency spacing is programmable from 165 to 660 kHz. The overall power dissipation of the RF transmitter is 500μ
W, a 10× improvement over previous INI VCO designs. This large improvement is due to the shift in process technology from 0.5-μ
m CMOS to a 0.6-μ
m BiCMOS process with a thick top metal layer. The minimum power dissipation of LC
oscillators required to sustain oscillation is a function of inductor losses [15
]. Using this low-resistance metal, it was possible to design a 26-nH inductor with quality factor of Q
= 11 at 900 MHz, dramatically decreasing the power dissipation of the circuit. Additionally, the use of bipolar npn transistors in the −gm
cell improves power dissipation by maximizing the design’s gm
ratio and reducing device-related parasitic capacitances.
To complete the wireless interface to the INI3 chip, custom printed circuit boards were designed to send power and commands and receive telemetry data (see ). The power board uses a class E power amplifier to create a ~60 V pk
2.765-MHz waveform from a 5 V supply and drive a 5.8-cm-diameter, 28-turn printed-circuit coil. The resulting ac magnetic field powers the INI3 chip. Techniques described in [16
] were used to optimize the power link. A USB link to a laptop PC allows the user to send command strings that modulate the amplitude of the coil voltage; the INI3 chip can be completely reprogrammed in less than 100 ms.
Custom circuit boards supporting wireless power and data link to INI3 chip. Left: 2.765-MHz inductive power/command unit with 5.8-cm printed-circuit coil. Right: 902–928 MHz RF telemetry receiver unit.
The telemetry receiver board implements a 900-MHz FSK demodulator with programmable center frequency and USB interface. Demodulated data are streamed to the PC at the INI3 transmission rate of 345.6 kb/s. PC software locates frame markers generated by the chip, checks parity bits, and decodes the data. A software interface displays the waveform digitized by the ADC at two time scales: a 100 ms window showing a continuously streaming waveform and a 2 ms window showing the most recent time-aligned spikes (see ). A third window plots a running graph of bit error rate (BER), which is calculated by checking the parity bits generated by the INI3 chip. If an ADC sample contains a parity error, its value may be interpolated from the previous and following samples to reduce glitches in the waveform. The bottom window displays spike rasters from all 100 spike detectors on the chip.
Fig. 7 Screenshot of telemetry receive software. Upper left windows show amplifier/ADC waveform at different time scales. Upper right window shows running plot of telemetry bit errors, and the bottom plot shows 100 spike rasters from on-chip spike detectors. (more ...)
To facilitate chip testing before complete integration to a UEA, we packaged several bare chip die in plastic quad flat pack (QFP) packages and soldered some of these to small circuit boards (see ). Due to space limitations around the periphery of the chip, only 20 of the 100 on-chip amplifiers are available in the packaged chips. shows the general configuration used for benchtop and in vivo experiments described in the remainder of this paper.
Wireless testing configuration for in vivo experiments using INI3 chip with one external capacitor. Power and commands are delivered wirelessly via inductive link; telemetry is received via 900 MHz antenna.