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Logo of nihpaAbout Author manuscriptsSubmit a manuscriptHHS Public Access; Author Manuscript; Accepted for publication in peer reviewed journal;
Solid State Electron. Author manuscript; available in PMC 2010 August 11.
Published in final edited form as:
Solid State Electron. 2008 June 1; 52(6): 899–908.
doi:  10.1016/j.sse.2008.01.025
PMCID: PMC2919744

Small-Signal Performance and Modeling of sub-50nm nMOSFETs with fT above 460-GHz


We have fabricated and tested the performance of sub-50nm gate nMOSFETs to assess their suitability for mixed signal applications in the super high frequency (SHF) band, i.e. 3–30GHz. For a 30nm×40 μm×2 device, we found fT =465GHz at Vds=2V, Vg=0.67V, which is the highest cut-off frequency reported for a MOSFET produced on bulk silicon substrate so far. However, our measurements of fmax and noise figure indicate that parasitics impose limitations on SHF operation. We also present a high-frequency ac model appropriate to sub-50nm gate length nanotransistors, which incorporates the effects of the parasitics. The model accurately accounts for measurements of the S and Y parameters in the frequency range from 1 to 50GHz.

Index Terms: Radio Frequency (RF) MOSFET, RF MOSFET modeling, High-Frequency, Mixed-Signal


Mobile/(broadband) wireless communications is changing everything. Portable communication devices like the cell phone, along with 3G, WLAN, Bluetooth® are spurring the demand for high frequency, mixed signal integrated circuits that are inexpensive, reliable and have a long battery life. CMOS technology can satisfy these demands. The relentless scaling of CMOS toward nanometer-scale gate lengths has produced MOSFETs with digital and RF performance that is suitable for mixed-signal applications.

The merit of a transistor depends on the circuit design. While large signal digital integrated circuits often use gate delay as a metric, the same loading conditions don’t generally apply to RF circuits.[1] Three (metrics)/figures-of-merit appropriate to small-signal RF performance are the cut-off frequency associated with the short-circuit current gain,


the maximum frequency of oscillation (where the unilateral power gain vanishes),


and the noise figure Fmin,


where gm is the transconductance, Cgs and Cgd are the gate-to-source and gate-to-drain capacitances, Rs is the parasitic source resistance, Rg is the (lumped) gate resistance, gds is the output conductance, W is the total gate width, n is an index that ranges from 1<n<2 depending on the transistor model (short or long channel), and K is a constant that depends on the technology. Ostensibly, improvements in fT follow from scaling of the gate length, Lg. There has been a progressive increase in fT to 330GHz for a 60nm gate length nMOSFET [25], which is comparable to observations in sub-100nm InP[6] HEMTs, but still inferior to reports on SiGe[7] and InP/InGaAs HBTs[810]. On the other hand, in MOS technology, fmax generally lags behind fT — the disparity can be accounted for by parasitics,[2,1113] such as Rg and gds that are not optimized in a core CMOS manufacturing process. With acceptable gain, the noise figure, Fmin, also has to be minimized to make effective use of CMOS technology for RF. Like fT, Fmin has been found to improve (diminish) with each technology generation[2], but just like fmax, Fmin also depends on parasitic elements that are sensitive to the gate bias and geometry.

Along with the RF performance, another prerequisite for the implementation of mixed circuits in CMOS is accurate, high frequency models for the MOSFET[1324] and passives. Specifically, the MOSFET model must accurately represent the power gain, input and output impedance and phase delay between the gate voltage and the drain current. A microwave table-based approach to modeling can be very accurate, but requires a large database obtained from numerous measurements and computationally intensive simulations—it becomes intractable for designing highly integrated CMOS communications circuits. Instead, a compact physics-based model is preferred, but a physics-based model has to be valid over a range of bias conditions, temperatures, and frequencies. Consequently, it has to account, not only for parasitic resistances and capacitances, but also for non-quasi-static (NQS) or distributed effects in the gate, substrate and channel resistances due to the channel propagation delay, and non-reciprocal capacitances that account for the different effect of the gate and drain on each other in terms of charging currents.[19,25]

Here, we report on the fabrication, testing and modeling of the RF performance of sub-50nm gate length nMOSFETs to assess their suitability for mixed signal applications in the super high frequency (SHF) band, i.e. 3–30GHz. Using a conventional process flow suitable for a digital technology, we fabricated nMOSFETs with gate lengths as short as 30nm, and then we measured the DC and RF performance. Following Rashkin[2628] we extended the usual de-embedding methodology[29] to account for additional access capacitances associated with metal interconnections running between the (SOLT) reference plane and the contacts to the drain, source and gate. With this refinement, we extracted an fT =465GHz from measurements of a 30nm×40μm×2(finger) nMOSFET taken in the frequency range 1GHz<f<50GHz at Vds=2V, Vg=0.67. This is the highest cut-off frequency reported for a MOSFET so far. It represents a substantial improvement over previous extrapolations using the same transistors (fT =290GHz) that do not account for the access capacitance.[30] However, our measurements of fmax≤135GHz and noise figure Fmin=0.9dB at 8GHz indicate that parasitics still impose limitations on SHF operation. The equivalent circuit that we developed to model the RF performance is based on Tsividis’s work[19] incorporating the effect of extrinsic and access parasitics and NQS. This model gives an accurate accounting of the measurements of the Y parameters in the frequency range from 1 to 50GHz and scales appropriately with the transistor layout.


We have produced sub-50nm nMOSFETs using a conventional process flow suitable for digital applications. The layout for the unit cell for RF-MOSFET uses a co-planar waveguide structure to facilitate the RF measurements with a gate that is folded into a multi-legged structure and contacted from one side of the channel. An example of a two-legged MOSFET is shown in Figure 1(a). The aspect ratio of the folded gate guarantees that the total gate resistance is determined by the length of the legs while the shared drain contact reduces the overall junction capacitance. Using this geometry, we expect fmax to scale closely with the length of the leg. An especially dramatic illustration of the performance that can be recovered through gate engineering like this is the recent demonstration by Tiemeijer et al. [12] of fmax = 150GHz obtained using a 180nm gate length CMOS foundry process that exhibits a cut-off frequency of only fT =70GHz on a resistive 10Ω-cm substrate.

Figure 1
(a) A scanning electron micrograph of a MOSFET tester (metal contacts to the Source, Gate, and Drain shown here). The cross section of the MOSFET (blue dashed line) is shown in Fig. (b). (b) A transmission electron micrograph of one finger of a nominally ...

A transmission electron micrograph of a cross-section through a representative MOSFET structure is shown in Figure 1(b). The transistors were fabricated using 90nm thick LOCOS isolation on float-zone (>800 Ohm-cm) wafers. A 30keV boron implant with a fluence of 5.0E13cm−2 was used to form the p-tub, and a 7keV boron implant at 1.5E13cm−2 was used to form the channel. Subsequently, a 1.3nm thick gate oxide was grown using rapid thermal oxidation, which was followed by the deposition of a 95nm thick in-situ phosphorus-doped polysilicon layer. The 30–50nm gate electrodes, defined by electron beam lithography in Sumitomo resist NEB31, were transferred into the poly using reactive ion etching without using a hard mask. The gate-etch stopped on the thin gate oxide without trenching. Following the definition of polysilicon gates, an arsenic implant at 2.5keV with a fluence of 3.0 × 1014cm−2 was used to form the shallow Source/Drain (S/D) extensions. Subsequently, a 30nm silicon nitride layer was deposited on top of a thin 10nm silicon dioxide layer and subsequently etched to create the sidewall spacers. A 47keV arsenic implant at 4 × 1015cm−2 was then used to define the S/D. The doping was activated using a rapid thermal anneal for 1 second at 1050°C in nitrogen with a 75°C/s ramp. Finally, we used a cobalt-salicide process to lower the gate and S/D resistance to about 8Ω/sq. The salicide consisted of the deposition of 5.0nm of Cobalt followed by a 30s@550°C and a 30s@750°C anneals for the formation of a highly conductive CoSi2 layer.

The back end of the process used 400nm of dielectric (TEOS) to isolate the 0.75μm aluminum coplanar waveguide structures (used for RF measurements) from the high-resistivity float-zone substrate. A 50nm silicon nitride layer prior to the TEOS deposition was used to facilitate the etching of 0.5μm vias by protecting the silicided gate and S/D extensions. After the vias to S/D and the gate were etched, a 30nm Ti + 80nm TiN layer was deposited and annealed at 700°C for 20s prior to aluminum deposition to serve as a diffusion barrier and aid the adhesion of the aluminum. Finally, before the metal contact lithography, 25nm of TiN was deposited to cap the aluminum.


We measured the dc current-voltage characteristics of MOSFETs fabricated this way. Typical results obtained for a gate length 45nm×20μm×2 (gate length × gate width × number of fingers) and Lg=30nm×40μm×2MOSFETs are shown respectively in Figures 2(a–c) and 2(d–f). For the 30nm gate, we found a drive current ID=1.9mA/μm at VDS =VG =2V and an off-state current of 310μA/μm, measured at VG=0V and VDS=2V, giving an Ion/Ioff=6. The maximum transconductance in the saturation region is gm = 0.94mS/μm, which is found at VDS =2V for VG= 0.67V. For the 45nm device, we observe a drive current ID=1.8mA/μm at VDS =VG= 2V with an off-state current of 55μA/μm, giving an Ion/Ioff=33. The maximum transconductance in the saturation region is gm = 1.1mS/μm at VDS = 2V and VG = 0.67V.

Figure 2
The drain, transconductance, and subthreshold characteristics measured in 30nm×40μm×2 (a–c) and 45nm×20μm×2 (d–f) nMOSFETs respectively. The drive current ID= 1.9mA/μm and 1.8mA/μm ...

From the subthreshold characteristic shown in Figures 2(c) and 2(f), we infer that short channel effects like drain induced barrier lowering and channel length modulation affect the device performance. In particular, the drain characteristic indicates a finite output resistance that can be represented by a lumped element of 30Ω in the intrinsic model for the MOSFET (see Table I). The short channel effects are especially evident in the 30nm device, which result in a reduced transconductance even though the gate length is smaller. Another detrimental factor may be the series resistance associated with the relatively thin (0.75μm) aluminum layer used for coplanar waveguide structure. This parasitic resistance may have an adverse effect on the transconductance, and consequently adversely affect both fT and fmax. The gate current measured in the 30nm×40μm×2 MOSFET is IG=4.9nA/μm when it is on, biased at VG=2V and VD=2V, and <28nA/μm when it is off, biased at VG=2V and VD=0V. Because of the small active area, the gate leakage current associated with quantum mechanical tunneling through the 1.3nm gate oxide does not affect the dc characteristics appreciably although it may contribute shot noise.[24]

(30nm×Wμm×2) Extracted MOSFET Parameters From Model


According to Tsividis[19], a physics-based model for the high frequency operation of a MOSFET can be separated into intrinsic and extrinsic contributions as illustrated in Figure 3. The intrinsic elements, which are inside the red broken line in Figure 3, are supposed to depend on the bias conditions and the geometry of the active area of the device. The intrinsic parameter, gm, represents the small-signal gate transconductance; gmb represents the substrate transconductance; and gds the output conductance. For nanometer-scale transistors the small signal model also has to account for tunneling between the gate electrode and the source and drain contacts, which is exponentially dependent on the voltage and oxide thickness. Two resistances, Rgst and Rgdt are used to represent the different currents associated with tunneling through the same 1.3nm thick gate oxide. To account for charge storage, we assume quasi-static operation and use the intrinsic capacitances Cgsi, Csbi, Cgdi and Cdbi required to represent the change in the gate and depletion charges. The capacitances are bias dependent and may not be reciprocal. Non-reciprocal effects, which are modeled by adding transcapacitances and a corresponding dependent current sources to accurately account for the charging current, are expected to affect the prediction of the transadmittances Y21 and Y12, although they are usually ignored for frequencies <50GHz.[25]

Figure 3
The compact equivalent circuit of a sub-50nm MOSFET. This model accounts for the NQS effect in the SHF region. The equivalent circuit of the intrinsic part of the transistor which was used to fit the measurements includes the pairs C1-R1 and C2-R2 to ...

The small-signal model for the drain current consists, not only of the contribution from the channel (drain-to-source), but also has a parasitic component due to impact ionization at high electric field that flows between the substrate and the drain. The role of the source in the above analysis will be played by the substrate instead. The parameters Rdbi and Cdbi, and Rsbi and Csbi reflect the substrate contribution. And finally, the nonquasi-static effects (NQS) in the intrinsic model (i.e. the finite charging time in the channel inversion layer due to the history of the voltage biases) are accounted for by using the voltage-control-current-sources (VCCS) connected in parallel with the intrinsic capacitances and admittances[19]. For example, the lag in the gate current behind a quickly varying drain signal is accounted for by parameters such as Rgdi and Cgdi. The corresponding parameters associated with a source excitation are Rgsi and Cgsi. The coefficients of the VCCS’s (gm and gmb) in Figure 3 would usually be complex, but following Tsividis we circumvented this complication by using the series combinations of R1 and C1, and R2 and C2 respectively (which are highlighted in red in Figure 3).[19] These simple circuit elements are chosen to draw a negligible current in comparison to the Rgsi and Cgsi, and Rbsi and Cbsi combinations.

In contrast with the intrinsic components, the extrinsic elements are supposed to be independent of bias, but scale with the active area of the device. At high frequency, the admittance of these extrinsic capacitances can be large compared to that of the intrinsic elements in parallel with them. Thus, a comprehensive small-signal model of the extrinsic effects must also include parasitic resistances and inductances. This is accomplished economically using only a few lumped elements. For example, as shown in Figure 4, the resistive material associated with the source, drain, and gate are represented respectively by the resistances, Rse, Rde, and Rge,. Rse and Rde, which include the losses associated with the metal contacts and the contact resistance associated with the source and drain implants and are inversely proportional to the gate width. The extrinsic gate resistance, Rge, includes both the resistance of the gate finger, which is proportional to the gate width, and the metallic losses associated with the connection of the gate to the co-planar waveguide (CPW) up to the reference plane. The contribution to Rge due to the series resistance of the silicide on top of the polysilicon layer is usually assumed to predominate according to Rge=rsW/3Lg, where rs is the sheet resistivity of the silicide.[11] (For aggressively scaled technologies there is an additional contact resistance that may have to be taken into account that is associated with the interface due to the Schottky contact between the silicide and polysilicon given by: Rgec=rC/WLg where rC is the contact resistivity.[31] For a typical transistor used in these experiments W≥5μm and Rge>Rgec~100Ω) The parasitic inductances are defined similarly. However, because of the nanometer-scale channel length and wide source-drain regions, the intrinsic and extrinsic inductances have values <1pH, and so they are negligible in the SHF band. Due to the size of the gate finger and gate resistance, we found it necessary for a good fit to include only the extrinsic gate inductance Lge.

Figure 4
(a) is a top-down view (SEM) of the coplanar waveguides used in conjunction with GND-Signal-GND (GSG) RF probes to measure the S-parameters of our device. The signal of port1 of the PNA is Gate, and the signal of port2 of the PNA is Drain. The SOLT calibration ...

We experimentally determined that there are additional parasitic couplings to account for between the metal wires outside the intrinsic region of the device, which can be adequately represented by capacitances that span the drain-source, gate-source and gate-drain terminals.[2628] In Figure 3, we denote these capacitances as Cdsee, Cgsee, and Cgdee, i.e. extrinsic-extrinsic elements which are independent of bias and proportional to the gate width. These elements do not account for the access admittances like Cda associated with the metal leads as illustrated in Figure 4, however. Although, the access admittances can be adequately represented by capacitances in parallel with these extrinsic-extrinsic capacitances, they scale differently. So, Figure 3 indicates that the access capacitances Cga and Cgda are summed with the corresponding extrinsic-extrinsic capacitances.


The RF performance from 50MHz to 50GHz of nanotransistors embedded in a CPW was measured using an Agilent E8364B PNA. To launch the signal from the RF probe tips to the device under test (DUT), a CPW is used in a ground-signal-ground configuration as shown in the micrograph of Figure 4. Because of the relative size of the device, parasitic elements associated with the contact pads, and interconnects cannot be neglected. So, the intrinsic performance of the transistor had to be de-embedded from the data.

We used Y-parameters to characterize the RF measurements. To obtain an accurate assessment of the Y-parameters, we used a two step procedure. First, using a full 2-port SOLT calibration,[26,29] we automatically subtracted the Y-parameters associated with on-wafer standards consisting of a short, an open, a load (nominally 50Ω, and a thru (SOLT) from the DUT measurements using the E8364B. (This extends the reference plane to the dotted line in Figure 4(b).) While this calibration technique is renowned for its accuracy[29], it does not account for the access admittances like Cda indicated in Figure 4(c) associated with the metal leads extending from the SOLT reference plane and to the source, drain and gate contacts. Since the MOSFET gate width does not extend into the ground plane of the CPW, (see Figure 4(b)), the access admittances can be adequately represented solely by capacitors.

The second step involves subtracting the admittance associated with the access capacitances from the imaginary part of the SOLT calibrated measurements of the Y-parameters. The access capacitances were inferred using a linear regression to determine the intercepts of the effective capacitance (Im[Y/ω]) versus gate width from measurements of the Y-parameters using extraction techniques based on the ColdFET and Inversion approximations.[25],[28] With the MOSFET biased OFF, (i.e. Vds=0V and Vg<Vt), the active area of the device can be neglected, and the imaginary part of the measured Y-parameters is the sum of the extrinsic capacitances and the access capacitances, i.e.


Equations 4(ac) are insufficient for discriminating between the access capacitances and the extrinsic (or intrinsic) capacitances. However, the extrinsic and extrinsic-extrinsic capacitances like Cdsee are directly proportional to the gate width, while the access capacitances are independent of W. Thus, by using the intercepts of a regression line through the effective capacitance Im(Y/ω) versus gate width, we can determine the access capacitances. Two deficiencies of this method are: 1) the capacitances obtained includes other capacitances such as the gate-to-source capacitance due to the enlarged region of the polysilicon used for contact access that is located on top of the LOCOS isolation oxide (usually negligible); and 2) there is additional error introduced by the regression equation.

Using Agilent’s Advanced Design System software to fit the model to the data, we arrived at the final estimates for the lumped elements represented in Figure 3. For example, we extracted the intrinsic and extrinsic parameters associated with 30nm×Wμm×2 and 45nm×Wμm×2 MOSFETs biased at Vds=2.0V and Vg at the maximum of the transconductance. Table I lists the values for all parameters in the compact model of the 30nm×Wμm×2 nMOSFET. These parameters are consistent with analytical estimates given by Tsvidis.[19] For example, from [19] we expect Cgsi~(2/3)Cox and Cgdi~0 and RgsiCgsi>RgdiCgdi, despite the observation that the fit is insensitive to the value of Rgdi. We find that without varying Rgsi, there is <1–2% change in the parameters and <50% change in the residual for 1Ω<Rgdi<2Rgsi.

Comparisons between the predictions of the model for the 30nm×40μm×2 and 45nm×10μm×2 MOSFETs using the parameters obtained from the extraction technique and the measurements are illustrated in Figures 5 and and6,6, respectively. Generally, we find very close correspondence between the Y-parameters calculated from the model and the measured data up to 50GHz. Measurements of both the real and imaginary parts of the Y-parameters follow the predictions of the model shown in Figure 3, even though nonreciprocal transcapacitances (such as Cgdi and Cdgi) are not included in the model, which was expected to make it difficult to accurately predict Im[Y21] and Im[Y12] at the same time.[25] Unlike the measurements obtained on 5, 10, and 20μm channel width MOSFETs, neither Im[Y21] nor Im[Y22] approach zero in the frequency range shown in Figures 5 and and6,6, which the model of Figure 3 attributes to the high gate resistance associated with the 40μm channel widths.

Figure 5
Comparison of the Y-parameters of the model and measured data for a 30nm×40μm×2 device from 1GHz to 50GHz. Both the real (gray lines) and imaginary (black lines) parts of the model are compared with the real (grey triangles) and ...
Figure 6
Comparison of the Y-parameters of the model and measured data for a 45nm×10μm×2 device from 1GHz to 50GHz. Both the real (gray lines) and imaginary (black lines) parts of the model are compared with the real (grey triangles) and ...

One advantage of this model of Figure 3 is economy. It contains fewer parameters than the distributed version[30], and yet it still accurately accounts for the measurements in the frequency range from 1GHz to 50GHz, and scales appropriately with geometry. While this model is compact, which facilitates IC design, the fit to the data deteriorates slightly compared to the distributed model.[30] The error function χ2, which is based on the sum of the squares of the residuals, is doubled from approximately 0.03 to approximately 0.05. This slight degradation of the fit, however, is imperceptible in the plots of the Y- parameters, the power gain and the current gain.

The extracted parameters match the results obtained from low frequency or dc measurements, and closely correspond to parameters estimated from the physical structure of the MOSFET. Figures 7(a) and (b) compare low frequency (dc) measurements of the effective gm, and gds, with the intrinsic parameters extracted from the model of Figure 3 in the low frequency limit (5 MHz). We find that the low frequency measurements generally correspond with the extracted parameters, except for a gate width of W=40μm where the model predicts larger values, beyond the error attributed to the fit. The discrepancies found for a gate width of W=40μm may be associated with the inability of the lumped element model to capture the distributed nature of the gate, source, drain and channel resistances. It is not observed for a distributed model for the gate.[30] A comparison of measurements of the intrinsic capacitance Cgsi and the extrinsic parameter Cdsee versus gate width are shown in Figures 7(c) and (d). To compare with the values extracted from the model (Fig. 3), we have estimated Cgsi from PADRE simulations of the transistor geometry. Cgsee was inferred from the measured Y-parameters using extraction techniques based on the ColdFET approximation.[25]

Figure 7
A comparison of parameters obtained from the model to parameters obtained from extraction based on the Y-parameter matrix and DC measurements. The triangles represent values obtained from measurements or estimates, while the solid line mark values obtained ...


Figure 8(a) illustrates the RF performance of 30nm×40μm×2 nMOSFETs biased at the transconductance maximum gm=0.94S/mm found at Vg=0.67V for Vds=2V. The performance is indicated by the short circuit current gain, h21, and Mason’s unilateral gain, U. Both h21, and U exhibit a nearly ideal single-pole response with frequency, and so we infer fT and fmax by extrapolating to unity gain at −20dB/decade from data in the range 40–50GHz. For the 30nm gate length MOSFET we find fT =465GHz as indicated in Figures 8(a). However, a similar extrapolation using a single pole response for data in the range 1–30GHz indicates that fT [congruent with]500GHz for the same MOSFET as shown in Figure 8(b). This discrepancy from the single-pole response observed above 30GHz is an indication of the difficulty realizing adequate calibration at the high frequency end of the PNA.

Figure 8
(a) Cutoff frequency, fT, of 30nm×40μm×2 inferred from a −20dB/dec extrapolation from the points in the 40–50GHz range and (b) the distribution of the cutoff frequency inferred at −20dB/dec from each point ...

A nMOSFET fT =465GHz is comparable to the best SiGe-BJT reported in literature so far.[6] On the other hand, the power gain performance measured by fmax=45GHz as shown in Figures 8(c) is reduced by a factor of 10 from the cutoff frequency. The degradation of fmax is an indication of the detrimental effect of parasitics indicated by Equation (2). Relying on the agreement between the model of Figure 3 and measured current and power gain shown in Figure 8(c), we infer that parasitic elements such as the gate resistance, Rge, and the series source and drain resistances, Rse and Rde, respectively adversely affect the power gain in the SHF band. Moreover, previous extrapolations based on the same measurements showed that fT =290GHz and fmax = 45GHz for the 30nm gate length.[30] The prior extrapolations reflect the detrimental effects of the access capacitances on the estimate of fT.

Figures 9(a) and (b) illustrate measurements of the RF performance in the same 30nm×40μm×2 and 45nm×20μm×2 nMOSFETs of Figure 2, showing the same trend in current and power gain. There is an improvement gleaned in the current gain from decreasing the channel length: i.e. the the 45nm device shows fT=350GHz while the 30nm MOSFET has an fT above 460GHz. Figure 9(c) summarizes the measured dependence of fT on the gate length inferred from top-down scanning electron microscopy (SEM) for devices with the same gate width. Within the error, we find that fT data is consistent with a 1/Lg dependence associated with short channel MOSFETs over the narrow range examined (30–50nm) as anticipated from Equation (1). The SEM measurements were found to be consistent with cross-sectional TEM assessments done on the same devices using focused ion beam milling to prepare the specimens. The error associated with the length measurement develops from variations in the gate length along the width of the device associated with the lithography and etching. The error associated with the estimate of fT develops mainly from errors in the measurement of the gain in the 40–50GHz band.

Figure 9
(a,b) Measurements of the RF performance of the 30nm×40μm×2 and 45nm×20μm×2 nMOSFETs shown in Fig. 2 fT and fmax were obtained at Vds=2V by extrapolating S-parameter-measurements in the 40–50GHz ...

Both gds and Rge increase as the gate length decreases, which has a detrimental effect on fmax. So, we anticipate that fmax~1/W as indicated in Equation (2), provided that gm, Rge, gds, Cgsi and Cgdi scale linearly with the gate width.[11] Figures 9(b) and (d) show two nMOSFETs of comparable gate length, but different gate widths: i.e. 45nm×20μm×2 and 46nm×5μm×2 respectively. As illustrated by a comparison of the two figures, devices with a shorter gate width deliver higher fmax without compromising fT. The 46nm×5μm×2 device of Figure 8(d) exhibits an fT=330GHz and fmax=135GHz, while the 45nm×20μm×2 device has fT=350GHz and fmax=77GHz. Devices with a larger gate length can potentially deliver higher fmax despite a reduction in fT since improvements in Rge and gds could compensate for the degradation. The slight degradation of fT measured in the device of Figure 9(d) is offset by a decrease in W, Rg, and Rds.

We methodically explored the dependence of fT and fmax on gate voltage, width and length. The measured gate voltage-bias dependence of fT and fmax is illustrated in Figure 9(e) for a 47nm×10μm×2 MOSFET. The observed dependence follows from the gate voltage dependence of the transconductance as indicated in Equations (1) and (2). Generally, for the devices we measured, both fT and fmax scale with gm in the range 0<Vg<1.7V. The measured dependence of fT and fmax on gate width is illustrated in Figure 9(f) for similar gate length nMOSFETs (47nm versus 48nm) with different gate widths (10μm versus 40μm, respectively). Notice that even though the peak values of fT 300GHz are nearly identical, the peak value of fmax for the 47nm×10μm×2 MOSFET is about 100GHz, while the peak value for the 48nm×40μm×2 is less than half that value, fmax=41GHz. Figure 9(g) summarizes the trends observed in fT and fmax as a function of the gate width for nominally 30nm gate length MOSFETs. fT increases as the gate width increases while fmax increases with decreasing W. The increase in fT with gate width W is due to both proximity corrections in the electron beam lithography and gate etch that generate a narrower gate length for larger gate widths. Figure 9(f) reports on devices that are nominally 30nm long.

Finally, to make effective use of CMOS technology for RF applications, the noise figure, Fmin, also has to be minimized with an acceptable associated gain. So, we examined the broadband noise performance in the SHF band. Figure 9(h) shows a linear frequency dependence of Fmin that we anticipated in Equation (3). Fmin is about 0.9dB at 8GHz. Generally, we find larger noise figure with increasing frequency—approaching 3dB for frequencies above 20GHz, which compares favorably to data reported in on 80nm nMOSFET at the same operating point.[2] According to Equation (3), we expect an improvement in the noise figure if the gate resistance improves. For this 47nm×10μm×2 nMOSFET at 8GHz we find a maximum available gain of 22dB with Fmin <1dB, while at 20GHz, we find a maximum available gain of 11dB with Fmin <3.5dB.


In summary, measurements of sub-50nm gate nMOSFETs reveal the highest RF performance of a nMOSFET so far. For a 30nm×40μm×2 device, we found fT >460GHz at Vds=2V, Vg=0.67V after accounting for access capacitances. However, measurements of fmax≤135GHz and noise figure indicate that parasitics adversely affect the circuit performance. Very accurate models of the measurements in the SHF band that account for non-quasi-static effects and incorporate parasitics elements indicate that the gate resistance and the source-drain limit the power gain.


We gratefully acknowledge support from the Air Force (FA9550-04-1-0214), NSF (CCR 01-21616) and ONR (N00014-03-0268). The Center for Microanalysis of Materials, supported by the DOE (DEFG02-91-ER45439), was instrumental in this work.


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Contributor Information

V. Dimitrov, University of Illinois, Urbana, IL 61801.

J. Heng, University of Illinois, Urbana, IL 61801.

K. Timp, University of Illinois, Urbana, IL 61801.

O. Dimauro, University of Illinois, Urbana, IL 61801.

R. Chan, University of Illinois, Urbana, IL 61801.

M. Hafez, University of Illinois, Urbana, IL 61801.

J. Feng, University of Illinois, Urbana, IL 61801.

T. Sorsch, University of Illinois, Urbana, IL 61801.

W. Mansfield, New Jersey Nanotechnology Consortium, Murray Hill, NJ 07974.

J. Miner, New Jersey Nanotechnology Consortium, Murray Hill, NJ 07974.

A. Kornblit, New Jersey Nanotechnology Consortium, Murray Hill, NJ 07974.

F. Klemens, New Jersey Nanotechnology Consortium, Murray Hill, NJ 07974.

J. Bower, New Jersey Nanotechnology Consortium, Murray Hill, NJ 07974.

R. Cirelli, New Jersey Nanotechnology Consortium, Murray Hill, NJ 07974.

E. J. Ferry, New Jersey Nanotechnology Consortium, Murray Hill, NJ 07974.

A. Taylor, New Jersey Nanotechnology Consortium, Murray Hill, NJ 07974.

M. Feng, University of Illinois, Urbana, IL 61801.

G. Timp, University of Illinois, Urbana, IL 61801.


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